PC87591L datasheet(132/437 Pages) NSC

132 / 437 page

Embedded Controller Modules (Continued)

www.national.com

132

Revision 1.07

Note: When CLK1, CLK2, CLK3 and CLK4 are all 0, this is interpreted as a shift mechanism reset. In this case, the PSTAT

PS/2 Input Signal Register (PSISIG)

The PSISIG register is an 8-bit read only register. It provides the current value of the PS/2 port signals.

Location: 00 FE8816

Type: RO

CLK1 (Enable Channel 1)

0: Forces the PSCLK1 pin low (0) and disables channel 0 of the shift mechanism.

1: Depends on whether or not the shift mechanism is enabled.

• When the shift mechanism is enabled (EN bit in PSCON register is set to 1), channel 1 of the PS/2 ports

is enabled.

• When the shift mechanism is disabled (EN bit in PSCON register is set to 0), the clock line output buffer

data is 1 (i.e., the signal is pulled high by the pull-up, if enabled, and may be pulled low by an external de-

vice).

CLK2 (Enable Channel 2). Same as bit 3 of this register (described above) but for channel 2.

CLK3 (Enable Channel 3). Same as bit 3 of this register (described above) but for channel 3.

WDAT4 (Write Data Signal Channel 4). Controls the data output to channel 4 data signal (PSDAT4). For more

information, see the description of bit 1 (above).

CLK4 (Enable Channel 4). Same as bit 3 of this register (described above) but for channel 4.

Bit

76543210

Name

RCLK4

RDAT4

RCLK3

RCLK2

RCLK1

RDAT3

RDAT2

RDAT1

Bit

Description

RDAT1 (Read Data Signal Channel 1). The current value of the channel 1 data signal (PSDAT1).

RDAT2 (Read Data Signal Channel 2). The current value of the channel 2 data signal (PSDAT2).

RDAT3 (Read Data Signal Channel 3). The current value of the channel 3 data signal (PSDAT3).

RCLK1 (Read Clock Signal Channel 1). When read, returns the current value of the channel 1 clock signal

(PSCLK1).

RCLK2 (Read Clock Signal Channel 2). When read, returns the current value of the channel 2 clock signal

(PSCLK2).

RCLK3 (Read Clock Signal Channel 3). When read, returns the current value of the channel 3 clock signal

(PSCLK3).

RDAT4 (Read Data Signal Channel 4). The current value of the channel 4 data signal (PSDAT4).

RCLK4 (Read Clock Signal Channel 4). When read, returns the current value of the channel 4 clock signal

(PSCLK4).

Bit

Description

PC87591L датащи(PDF) 132 Page - National Semiconductor (TI)

PC87591L датащи(HTML) 132 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL