PC87591L datasheet(128/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Revision 1.07

After each of the next seven falling edges of the clock line, one more data bit (bits 1 through 7) is driven on the data line of

the active channel (either PSDAT1, PSDAT2, PSDAT3 or PSDAT4).

On the ninth falling edge of the clock, the parity bit is output. The parity bit is high (1) if the number of bits with a value of 1

in the transmitted data was even (i.e., odd parity).

The tenth falling edge causes a 1 to be output as a stop bit. The data signal remains high to allow the PS/2 device to send

the line control bit.

The auxiliary device then completes the transfer by sending the line-control bit. The line-control bit, is identified by the data

signal being low after the 11th falling edge of the clock.

End of Transmission

The End-Of-Transmission state is entered when the line-control bit is detected. In response, the shift mechanism holds all

clock signals low, and if the internal pull-up is enabled, all data signals are pulled high by the internal pull-up.

The End-Of-Transaction flag (EOT in PSTAT register) is set to indicate that the transmit operation was completed; in addi-

tion, if EOTIE bit in PSIEN register is set, the interrupt signal to the ICU is set high.

The shift mechanism stays at this state until being reset.

Figure 43 illustrates the transmit byte sequence, as defined by the PS/2 standard.

Transfer Abort

At each stage of a receive or transmit operation, the transaction can be aborted by clearing all four channel enable bits

(CLK4-1) in PS/2 Output Signal register (PSOSIG) to 0. This resets the shifter state machine and puts it in the Enabled In-

active state. If the shift mechanism is in Transmit Inactive or Transmit Idle state, WDAT4-1 bits should also be set.

4.6.5

PS/2 Interface Registers

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

CLK

DATA

Bit 0

Parity Bit

Stop Bit

Start Bit

1st

CLK

2nd

CLK

9th

CLK

11th

CLK

I/O

Inhibit

10th

CLK

Figure 43. PS/2 Transmit Data Byte Timing

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