PC87591L datasheet(125/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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4.6.4

Operating With the Shift Mechanism Enabled

The shift mechanism is designed to off load the bit level handling of the data transfer from the firmware to a hardware

scheme; this improves system tolerance to interrupt latency. The mechanism includes a shift register and a state machine

that controls the PS/2 protocol.

Figure 41 illustrates the shift mechanism PS/2 data transfer sequence. There are three basic modes: Disabled, Receive and

Transmit. Different states in each mode define the progress of the data transfer. The rest of this section details the use of

the shift mechanism for implementing a PS/2 data transfer.

Reset the Shift Mechanism

Clearing either the shift mechanism enable bit (EN = 0 in PSCON register) or all the channels’ clock bits (CLK4-1 = 0) resets

the shift mechanism. In this state, PSTAT register is cleared (0016), and the state of the PS/2 clock and data signals

(PSCLK4-1 and PSDAT4-1) is set according to the value of their control bits (CLK4-1 and WDAT4-1, respectively).

When the shift mechanism is reset while in an unknown state or while in Transmit Idle state, the firmware should set (1)

WDAT4-1 before the shift mechanism is reset.

Before disabling the shift mechanism, the software should clear (0) CLK4-1 to prevent glitches on the clock signals.

Enable the Shift Mechanism

To enable the shift mechanism, verify that PSOSIG register is set to 4716 and then set (1) EN bit in PSCON register. This

puts the shift register state machine in Receive Inactive or Transmit Inactive state (XMT is 0 or 1, respectively, in PSCON

register). In either of these states, the clock signals (PSCLK4-1) are low and the data signals PSDAT4-1 are either floating

or pulled high.

PS/2 Reset

XMT = 0

XMT = 1

Start Bit

Detected

XMT = 1

EN = 1 and

EN = 0

Disabled

Receive

Inactive

XMT = 0

EN = 1 and

Transmit

Idle

Transmit

Active

Line Control

Bit Detected

End of

Transmission

or CLK4 = 1

Start Bit

Detected

Receive

Idle

CLK1, CLK2, CLK3

Receive

Active

Stop Bit

Detected

End of

Reception

and/or CLK4 = 1

Transmit Mode

Receive Mode

EN = 0

CLK1, CLK2, CLK3

and CLK4 = 0

CLK1, CLK2, CLK3

and CLK4 = 0

Transmit

Inactive

Figure 41. Shift Mechanism State Diagram

CLK1, CLK2, CLK3

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