PC87591L datasheet(127/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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End of Receive

When the stop-bit is detected, the shift mechanism enters the “End-Of-Reception” state. In this state, the shift mechanism:

●

Disables all the clock signals by forcing them low

●

Sets End-Of-Transaction status bit (EOT = 1 in PSTAT register)

●

If EOTIE bit in PSTAT register is set, it asserts (1) the interrupt signal to the ICU.

The shift mechanism stays in this state until it is reset.

Figure 42 illustrates the receive byte sequence, as defined by the PS/2 standard.

Transmit Mode

Transmit Inactive

When the shift mechanism is enabled and XMT bit in PSCON register is set (1):

●

The shift mechanism enters Transmit mode in Transmit Inactive state with all clock signals low and data signals high

(PSOSIG = 4716).

●

The ﬁrmware writes the data to be transmitted to the PS/2 data register (PSDAT).

●

The data line of the channel to be transmitted is forced low by the ﬁrmware clearing its data bit (WDAT4-1 for chan-

nels 4-1, respectively).

Transmit Idle

The Transmit Idle state can be entered by setting the channel enable bit (CLK4-1 for channel 4-1, respectively). This enables

the channel to be used for transmission. In this state, the shift-mechanism sets the clock of the enabled channel high (1)

while the data line of that channel is held low and waits for a start bit. When a PS/2 device senses the clock signal high with

the data signal low, it identifies a transmit request from the PC87591x.

The three channels not in use are disabled by forcing “0” on their clock lines.

Start Bit Detection

The start bit is identified by a falling edge on the clock signal while the data signal is low (0).

When a start bit is detected, data transmission begins by outputting bit 0 (LSB) of the transmitted data and setting data bits

WDAT4-1 in PSOSIG register. This allows bit 0 of the transmitted data to be output on the PS/2 data signal (PSDAT1,

PSDAT2, PSDAT3 or PSDAT4, according to the active channel).

In addition, the hardware sets the SOT bit (to 1) and stores the active channel number in ACH field, indicating transmission

of the start bit in PSTAT register. Note that if SOTIE bit in PSIEN register is set, an interrupt signal to the ICU is set high.

The firmware can use this interrupt to start a time-out timer for the data transfer.

Transmit Active

After identifying the start bit, the shift mechanism enters the Transmit Active state. The clock signal of the selected device

(PSCLK1, PSCLK2, PSCLK3 or PSCLK4) sets the data bit rate.

CLK

DATA

Bit 0

Parity Bit

Stop Bit

Start Bit

1st

CLK

2nd

CLK

10th

CLK

11th

CLK

Figure 42. PS/2 Receive Data Byte Timing

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