PC87591L datasheet(124/437 Pages) NSC

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Revision 1.07

Power Modes

The PS/2 interface is active only when the PC87591x is in Active mode. The shift mechanism should be disabled before

entering Idle mode. In Idle mode, the state of output signals cannot be changed (i.e., the firmware cannot write to PSOSIG

When the PC87591x needs to wake up on a Start bit detection by the MIWU, the PS/2 channels that may serve as wake-up

event sources must be enabled before entering Idle mode. To enable them, set to 1 their corresponding CLK bits in PSOSIG

The MIWU module can be used to identify a start bit in Idle mode and to return the PC87591x to Active mode. The MIWU

receives PSCLK4-1 and PSDAT4-1 signals as inputs (see Table 17 on page 105). The MIWU should be programed to iden-

tify a falling edge on the clock or data lines of the enabled channels. In this configuration, a start bit causes the PC87591x

to switch from Idle mode to Active mode. Once Active mode is reached, the firmware should cancel the transaction just start-

ed and then enable re-transmission of the information by the device.

PS/2 Interface Operation

The PS/2 interface has two basic operating methods: with the shift mechanism disabled and with the shift mechanism en-

abled. The following sections describe how to use the PS/2 interface with each of these operating methods.

4.6.3

Operating With the Shift Mechanism Disabled

The shift mechanism is disabled when EN bit in PSCON register is cleared (0). In this state, the PS/2 clock and data signals

are controlled by the firmware, which performs the PS/2 protocol by manipulating the PS/2 clock and data signals.

Clock Signal Control

CLK4-1 bits in PSOSIG register control the value of the respective clock signals (PSCLK4-1). When one of these bits is

cleared (0), the relevant pin is held low. When set (1), the open-drain output is open and the respective clock signal is either

floating or held high by the pull-up. In this case, an external device can force the respective clock signal low.

When reading PSISIG register, bits RCLK4-1 indicate the current state of the corresponding clock signal.

Data Signal Control

WDAT4-1 bits in PSOSIG register control the value of the respective data signals (PSDAT4-1). When one of these bits is

cleared (0), the relevant data signal is held low. When set (1), the open-drain output is open and the respective data signal

is held high by the pull-up. In this case, an external device can force the respective data signal low.

When reading PSISIG register, bits RDAT4-1 indicate the current state of the corresponding data signal.

Interrupt Generation

When DSMIE bit in PSIEN register is set (1), the clock input signals are connected to the Interrupt Control Unit (ICU) for an

interrupt driven PS/2 protocol. The four interrupts that are generated are PSINT4-1 for channels 4-1, respectively.

The ICU should be programed to detect a falling edge on each of the clock signals. Disabling a channel by writing 0 to the

clock control signals (CLK4-1) may cause a falling edge on a clock signal. When such an interrupt is not desired, clear the

clock control bit (0); then clear the respective pending bit in the ICU (or in the MIWU, for PSINT4). This should be done while

interrupts are disabled. For more details about the ICU, see Section 4.3 on page 98.

EOT bit (PSTAT)

SOT bit (PSTAT)

PSCLK1

PSCLK3

PSCLK2

EOTIE bit (PSIEN)

SOTIE bit (PSIEN)

PSINT1

PSINT2

PSINT3

Figure 40. PS/2 Interface Interrupt Signals

PSCLK4

DSMIE bit (PSIEN)

PSINT4*

* Use PSCLK4 in the MIWU.

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