PC87591L datasheet(123/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Quasi-Bidirectional Drivers

The quasi-bidirectional drivers have an open-drain output (Q2), an internal pull-up (Q3) and a low-impedance pull-up(Q1).

Q2 pulls the signal low whenever the output buffer data is “0”. The weak pull-up (Q3) is active whenever the output buffer

data is “1” and WPUEN in PSCON register is set (1). The low impedance pull-up is active whenever the PC87591x changes

the output data buffer from “0” to “1”, thereby reducing the low-to-high transition time. The length of time that the low-imped-

ance pull-up is active is determined by HDRV field in PSCON register. A schematic description of this output driver appears

in Figure 39.

Interrupt Signals

The firmware can use an interrupt-driven scheme to implement the PS/2 device interface. When the shift mechanism is not

in use, four interrupts are available (PSINT4-1), one for each channel. (PSINT4 is not connected to the ICU as a separate

input, the MIWU PSCLK4 input should be used instead). When the shift mechanism is in use, only one interrupt signal is

used (PSINT1). More details on the use of the interrupts are provided in Section 4.6.4 on page 125. Figure 40 illustrates the

interrupt scheme with the associated enable bits.

Channel 4

Channel 3

Channel 1

Channel 2

Shift Mechanism

EN1

PSCLK1

PSDAT1

DATO1

DATI1

CLKO1

CLKI1

EN2

DATO2

DATI2

CLKO2

CLKI2

EN3

DATO3

DATI3

CLKO3

CLKI3

CLK1

WDAT1

RCLK1

RDAT1

ENSM

PS/2 I/F

Registers

Figure 38. PS/2 Interface Functional Diagram

EN4

DATO4

DATI4

CLKO4

CLKI4

+VCC

Rising Edge

Detector

Output Buffer Data

Input Buffer Data

Figure 39. Quasi-Bidirectional Buffer

WPUEN

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