PC87591L datasheet(197/437 Pages) NSC

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Embedded Controller Modules (Continued)

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At each clock cycle, the slave can stall the master while it handles the previous data or prepares new data. The slave does

this, for each bit transferred or on a byte boundary, by holding SCLn low to extend the clock low period. Typically, slaves

extend the first clock cycle of a transfer if a byte read has not yet been stored or if the next byte to be transmitted is not yet

ready. Some microcontrollers with limited hardware support for the ACCESS.bus extend the access after each bit, thus al-

lowing the software time to handle this bit.

The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated, the bus

is considered busy. It retains this status for a given amount of time after a Stop Condition is generated. A high-to-low tran-

sition of the data line (SDAn) while the clock (SCLn) is high indicates a Start Condition. A low-to-high transition of the SDAn

line while the SCLn is high indicates a Stop Condition (Figure 70).

In addition to the first Start Condition, a Repeated Start Condition can be generated in the middle of a transaction. This allows

either another device to be accessed or a change in the direction of the data transfer.

Acknowledge Cycle

The Acknowledge cycle consists of two signals:

●

Acknowledge Clock pulse is sent by the master with each byte transferred

●

Acknowledge signal is sent by the receiving device (Figure 71)

The master generates the Acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases

the SDAn line (permitting it to go high) to allow the receiver to send the Acknowledge signal.The receiver pulls down the

SDAn line during the Acknowledge clock pulse, thus signalling that it has correctly received the last data byte and is ready

to receive the next byte. Figure 72 illustrates the Acknowledge cycle.

SDAn

SCLn

Start

Condition

Stop

Condition

Figure 70. Start and Stop Conditions

Start

Condition

Stop

Condition

SDAn

SCLn

MSB

ACK

12 3 - 6

3 - 8

Acknowledge Signal

from Receiver

Byte Complete

Interrupt within

Receiver

Clock Line Held

Low by Receiver

while Interrupt

is Serviced

Figure 71. ACCESS.bus Data Transaction

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