PC87591L datasheet(196/437 Pages) NSC

196 / 437 page

Embedded Controller Modules (Continued)

www.national.com

196

Revision 1.07

4.13 ACCESS.BUS (ACB) INTERFACE

The PC87591x includes two ACCESS.bus interface modules. The registers of each module are prefixed with ACBn, where

‘n’ is module number 0 or 1. The signal names are suffixed with ‘n’.

Each ACCESS.bus (ACB) interface is a two-wire serial interface that is compatible with the ACCESS.bus physical layer. It

is also compatible with Intel’s SMBus and Philips’ I2C bus. The module can be configured as either a bus master or slave

and can maintain bidirectional communication with multiple master and slave devices. As a slave device, the ACB module

may issue a request to become the bus master.

The ACB interface provides full support for a two-wire ACCESS.bus synchronous serial interface. It permits easy interfacing

to a wide range of low-cost memories and I/O devices, including EEPROMs, SRAMs, timers, A/D converters, D/A convert-

ers, clock chips and peripheral drivers.

4.13.1 Features

●

ACCESS.bus, SMBus and I2C compliant

●

ACCESS.bus master

●

ACCESS.bus slave

— One or two user-deﬁned addresses

— Global (broadcast) address

— ARP address

●

Supports polling- or interrupt-controlled operation

●

Generates a wake-up signal on detection of a Start Condition in Power-Down mode

●

Optional internal pull-up on SDAn and SCLn pins

4.13.2 Functional Description

The ACCESS.bus protocol uses a two-wire interface for bidirectional communication between the ICs connected to the bus.

The two interface lines are the Serial Data Line (SDL) and the Serial Clock Line (SCLn). These lines should be connected

to a positive supply via a pull-up resistor and remain high even when the bus is idle.

The ACCESS.bus protocol supports multiple master and slave transmitters and receivers. Each IC has a unique address

and can operate as a transmitter or a receiver. Some peripherals are receivers only.

During data transactions, the master device initiates the transaction, generates the clock signal and terminates the transac-

tion. For example, when the ACB initiates a data transaction with an attached ACCESS.bus-compliant peripheral, the ACB

becomes the master. When the peripheral responds and transmits data to the ACB, their master/slave (data transaction ini-

tiator and clock generator) relationship is unchanged even though their transmitter/receiver functions are reversed.

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCLn). Con-

sequently, throughout the clock’s high period, the data should remain stable (see Figure 69). Any change on the SDAn line

while SCLn is in high state during a transaction causes the current transaction to abort. New data should be sent during the

low SCLn state. This protocol permits a single data line to transfer both command/control information and data, using the

synchronous serial clock.

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condi-

tion to terminate the transaction. Each byte is transferred with the most significant bit first. An Acknowledge signal must fol-

low each byte (8 bits). The following sections provide further details of this process.

SDAn

SCLn

Data Line

Stable:

Data Valid

Change

of Data

Allowed

Figure 69. Bit Transfer

PC87591L датащи(PDF) 196 Page - National Semiconductor (TI)

PC87591L датащи(HTML) 196 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL