PC87591L datasheet(200/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Revision 1.07

Master Transmit

After becoming the bus master, the device can start transmitting data on the ACCESS.bus.

To transmit a byte, the software should:

1. Check that BER and NEGACK bits in ACBnST register are cleared and SDAST bit is set. In addition, if STASTRE bit in

ACBnCTL1 register is set, make sure that STASTR bit in ACBnST register is cleared.

2. Write the data byte to be transmitted to ACBnSDA register.

When the slave responds with a negative acknowledge, NEGACK in ACBnST register is set and SDAST in ACBnST register

remains cleared. In this case, if INTEN bit in ACBnCTL1 register is set, an interrupt is sent to the core.

Master Receive

After becoming the bus master, the device can start receiving data on the ACCESS.bus.

To receive a byte, the software should:

1. Check that SDAST bit in ACBnST register is set and BER bit is cleared. In addition, if STASTRE bit in ACBnCTL1 register

is set, make sure that STASTR in ACBnST register is cleared.

2. If the next byte is the last byte that should be read, set ACK bit in ACBnCTL1 register to 1. This causes a negative ac-

knowledge to be sent.

3. Read the data byte from ACBnSDA register.

Master Stop

To end a transaction, set STOP in ACBnCTL1 register before clearing the current stall flag (i.e., SDAST, NEGACK or STAS-

TR in ACBnST register). This causes the module to send a Stop Condition immediately and to clear STOP in ACBnCTL1

is set to 1).

Master Bus Stall

The ACB module can stall the ACCESS.bus between transfers while waiting for the core’s response. The ACCESS.bus is

stalled by holding the SCLn signal low after the acknowledge cycle. Note that this is interpreted as the start of the following

bus operation. The user must make sure that the next operation is prepared before the flag that causes the bus stall is

cleared.

The flags that can cause a bus stall in Master mode are:

●

Negative acknowledge after sending a byte (NEGACK in ACBnST register is set to 1).

●

SDAST in ACBnST register is set to 1.

●

STASTRE in ACBnCTL1 register is set to 1 after a successful start (STASTR in ACBnST is set to 1).

Repeated Start

A repeated start is performed when the PC87591x is already the bus master (MASTER in ACBnST register is set). In this

case, the ACCESS.bus is stalled and the ACB module awaits core handling due to a negative acknowledge (NEGACK in

ACBnST register is set to 1), an empty buffer (SDAST in ACBnST is set to 1) and/or a stall after start (STASTR in ACBnST

is set to 1).

For a repeated start:

1. Set START in ACBnCTL1 register to 1.

2. In Master Receive mode, read the last data item from ACBnSDA.

3. Follow the address send sequence, as described in “Sending the Address Byte” on page 199.

4. If the ACB is awaiting handling because STASTR in ACBnST is set to 1, clear it only after writing the requested address

and direction to ACBnSDA.

Master Error Detection

The ACB detects an illegal Start or Stop Condition (i.e., a Start or Stop Condition within the data transfer or the acknowledge

cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal condition is detected, BER is set and Master mode is

exited (MASTER in ACBnST register is cleared).

Bus Idle Error Recovery

When a request to become the active bus master or a restart operation fails, BER in ACBnST register is set to indicate the

error. In some cases, both the PC87591x and the other device may identify the failure and leave the bus idle. In this case,

the start sequence may not finish and the ACCESS.bus may remain deadlocked.

To recover from deadlock, use the following sequence:

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