PC87591L datasheet(193/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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All DAC channels are automatically disabled when entering Idle mode if ENIDLE bit in DACCTRL register is cleared to 0.

This happens regardless of the state of DACENn (n=0 to 3) bit in DACCTRL register. In this case, the DA0-3 outputs drive

0V.

If the ENIDLE bit is set to 1, entering the Idle mode does not affect DAC operation, and DA0-3 outputs drive the voltage level

set by DACDATn (n=0 to 3) registers.

4.12.5 DAC Registers

The DAC interfaces with the core using one control and four data registers. These registers are mapped to the core address

space, as defined in Appendix A on page 408.

DAC Register Map

DAC Control Register (DACCTRL)

This register controls the operation of the DAC module. DACCTRL is cleared (0016) on reset.

Location: 00 FF4016

Type: R/W

Mnemonic

Type

DACCTRL

DAC Control

R/W

DACDAT0

DAC Data Channel 0

R/W

DACDAT1

DAC Data Channel 1

R/W

DACDAT2

DAC Data Channel 2

R/W

DACDAT3

DAC Data Channel 3

R/W

Bit

76543210

Name

Reserved

ENIDLE

DACEN3

DACEN2

DACEN1

DACEN0

Reset

00000000

Bit

Description

DACEN0 (DAC Channel 0 Enable). Enables the DAC channel. The DA0 output pin drives a voltage level,

according to the value written into the corresponding DACDAT0 register.

When cleared, the DA0 output pin drives 0V.

0: Disabled (default)

1: Enabled

DACEN1 (DAC Channel 1 Enable). Same as DACEN0 bit description, using DA1 output and DACDAT1

DACEN2 (DAC Channel 2 Enable). Same as DACEN0 bit description, using DA2 output and DACDAT2

DACEN3 (DAC Channel 3 Enable). Same as DACEN0 bit description, using DA3 output and DACDAT3

ENIDLE (Enable in Idle). Controls the DAn (n=0 to 3) outputs in Idle mode.

0: Disabled - DAn outputs drive 0V (default)

1: Enabled - DAn outputs according to DACENn bits and DACDATn registers

7-5

Reserved.

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