PC87591L datasheet(198/437 Pages) NSC

198 / 437 page

Embedded Controller Modules (Continued)

www.national.com

198

Revision 1.07

“Acknowledge After Every Byte” Rule

The master generates an Acknowledge clock pulse after each byte transfer. The receiver sends an Acknowledge signal after

every byte is received.

There are two exceptions to the “acknowledge after every byte” rule:

●

When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging (negative

acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the Acknowledge clock

pulse (generated by the master), but the SDAn line is not pulled down.

●

When the receiver is full or otherwise occupied, or if a problem occurs, it sends a negative acknowledge to indicate

that it cannot accept additional data bytes.

Addressing Transfer Formats

Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave

being addressed. The slave device should send an Acknowledge signal on the SDAn line once it recognizes its address.

The address consists of the first seven bits after a Start Condition. The eighth bit contains the direction of the data transfer

(R/W). A low-to-high transition during a SCLn high period indicates the Stop Condition and ends the transaction of SDAn

(Figure 73).

When the address is sent, each device in the system compares this address with its own. If there is a match, the device

considers itself addressed and sends an Acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the

device acts as a transmitter or a receiver.

The I2C bus protocol allows a general call address to be sent to all slaves connected to the bus. The first byte sent specifies

the general call address (0016); the second byte specifies the general call meaning (for example, “Write slave address by

software only”). Slaves that require data acknowledge the call and become slave receivers; other slaves ignore the call.

Start

Condition

SCLn

12 3 - 6

Transmitter Stays Off the

Bus During the

Acknowledge Clock

Acknowledge

Signal from Receiver

Figure 72. ACCESS.bus Acknowledge Cycle

Data Output

Transmitter

Data Output

Receiver

Start

Condition

Stop

Condition

SDAn

SCLn

1 - 7

Address R/W ACK

Data

ACK

Data

ACK

Figure 73. A Complete ACCESS.bus Data Transaction

PC87591L датащи(PDF) 198 Page - National Semiconductor (TI)

PC87591L датащи(HTML) 198 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL