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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P89LPC932 датащи(PDF) 35 Page - NXP Semiconductors |
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P89LPC932 датащи(HTML) 35 Page - NXP Semiconductors |
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35 / 60 page  Philips Semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80C51 core Product data Rev. 04 — 06 January 2004 35 of 60 9397 750 12379 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 8.21 Serial Peripheral Interface (SPI) The P89LPC932 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection. The SPI interface has four pins: SPICLK, MOSI, MISO and SS: • SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions. • SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figures 16 through 18. Fig 15. SPI block diagram. 002aaa497 CPU clock DIVIDER BY 4, 16, 64, 128 SELECT CLOCK LOGIC SPI CONTROL REGISTER READ DATA BUFFER 8-BIT SHIFT REGISTER SPI CONTROL SPI STATUS REGISTER SPI clock (master) S M S M M S MISO P2.3 MOSI P2.2 SPICLK P2.5 SS P2.4 SPI interrupt request internal data bus MSTR SPEN clock |
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