P89LPC932 datasheet(22/60 Pages) PHILIPS

22 / 60 page

Philips Semiconductors

P89LPC932

8-bit microcontroller with accelerated two-clock 80C51 core

Product data

Rev. 04 — 06 January 2004

22 of 60

9397 750 12379

8.12 I/O ports

The P89LPC932 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1and 2

are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available

depends upon the clock and reset options chosen, as shown in Table 6.

8.12.1

Port conﬁgurations

All but three I/O port pins on the P89LPC932 may be conﬁgured by software to one of

four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port

outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each

port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be conﬁgured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

open-drain.

8.12.2

Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the

need to reconﬁgure the port. This is possible because when the port outputs a logic

HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the

pin is driven LOW, it is driven strongly and able to sink a fairly large current. These

features are somewhat similar to an open-drain output except that there are three

pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC932 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional

mode, if a user applies 5 V on the pin, there will be a current ﬂowing from the pin to

VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional

mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch

suppression circuit.

8.12.3

Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the

pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be

used as a logic output, a port conﬁgured in this manner must have an external

pull-up, typically a resistor tied to VDD.

An open-drain port pin has a Schmitt-triggered input that also has a glitch

suppression circuit.

Table 6:

Number of I/O pins available

Clock source

Reset option

Number of I/O pins

(28-pin package)

On-chip oscillator or watchdog oscillator

No external reset (except during power-up)

External RST pin supported

External clock input

No external reset (except during power-up)

External RST pin supported

Low/medium/high speed oscillator

(external crystal or resonator)

No external reset (except during power-up)

External RST pin supported

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