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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P89LPC932 датащи(PDF) 29 Page - NXP Semiconductors |
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P89LPC932 датащи(HTML) 29 Page - NXP Semiconductors |
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29 / 60 page  Philips Semiconductors P89LPC932 8-bit microcontroller with accelerated two-clock 80C51 core Product data Rev. 04 — 06 January 2004 29 of 60 9397 750 12379 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 8.18.7 Alternating output mode In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle. 8.18.8 PLL operation The PWM module features a Phase Locked Loop that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher. The PLL is fed an input signal of 0.5 - 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor of 1-16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as shown in Equation 1. (1) Where: N is the value of PLLDV3:0. Since N ranges in 0 - 15, the CCLK frequency can be in the range of PCLK to PCLK ⁄ 16. Fig 9. Symmetrical PWM. TOR2 COMPARE VALUE TIMER VALUE NON-INVERTED INVERTED 002aaa535 0 Fig 10. Alternate output mode. TIMER VALUE 002aaa536 0 TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) PWM OUTPUT A (or C) (P2.6) PWM OUTPUT B (or D) (P1.6) PLL frequency PLCK N1 + () ------------------ = |
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