VT82C596B datasheet(77/96 Pages) ETC

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VT82C596B

Revision 0.3 June 17, 1999

-71-

Function 3 Registers - Power Management and SMBus

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I/O Offset 5-4 - Power Management Control .................RW

15-14 Reserved

........................................ always reads 0

Sleep Enable (SLP_EN)...................... always reads 0

This is a write-only bit; reads from this bit always

return zero.

Writing a one to this bit causes the

system to sequence into the sleep (suspend) state

defined by the SLP_TYP field.

12-10 Sleep Type (SLP_TYP)

000 Normal On

001 Suspend to DRAM

010 Suspend to Disk (also called Soft Off). The

VCC power plane is turned off while the

VCCSUS and VCCRTC planes remain on.

011 Reserved

100 Power On Suspend without Reset

101 Power On Suspend with CPU Reset

110 Power On Suspend with CPU/PCI Reset

111 Reserved

In any sleep state, there is minimal interface between

powered and non-powered planes so that the effort

for hardware design may be well managed.

9-3

Reserved

........................................ always reads 0

Global Release (GBL_RLS) ............ WO, default = 0

This bit is set by ACPI software to indicate the

release of the SCI / SMI lock. Upon setting of this

bit, the hardware automatically sets the BIOS_STS

bit.

The bit is cleared by hardware when the

BIOS_STS bit is cleared by software. Note that the

setting of this bit will cause an SMI to be generated if

the BIOS_EN bit is set (bit-5 of the Global Enable

Bus Master Reload (BMS_RLD)............. default = 0

This bit is used to enable the occurrence of a bus

master request to transition the processor from the C3

state to the C0 state.

0SCI Enable (SCI_EN)............................... default = 0

Selects the power management event to generate

either an SCI or SMI:

Generate SMI

Generate SCI

Note that certain power management events can be

programmed individually to generate an SCI or SMI

independent of the setting of this bit (refer to the

General Purpose SCI Enable and General Purpose

SMI Enable registers at offsets 22 and 24).

Also,

TMR_STS & GBL_STS always generate SCI and

BIOS_STS always generates SMI.

I/O Offset 0B-08 - Power Management Timer ............... RW

31-24 Extended Timer Value (ETM_VAL)

This field reads back 0 if the 24-bit timer option is

selected (Rx41 bit-3).

23-0 Timer Value (TMR_VAL)

This read-only field returns the running count of the

power management timer. This is a 24/32-bit counter

that runs off a 3.579545 MHz clock, and counts while

in the S0 (working) system state. The timer is reset to

an initial value of zero during a reset, and then

continues counting until the 14.31818 MHz input to

the chip is stopped. If the clock is restarted without a

reset, then the counter will continue counting from

where it stopped.

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