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VT82C596B датащи(PDF) 48 Page - List of Unclassifed Manufacturers

номер детали VT82C596B
подробное описание детали  PCI INTEGRATED PERIPHERAL CONTROLLER
PDF  96 Pages
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производитель  ETC [List of Unclassifed Manufacturers]
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VT82C596B датащи(HTML) 48 Page - List of Unclassifed Manufacturers

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VT82C596B
Revision 0.3 June 17, 1999
-42-
PCI Function 0 Registers - PCI-to-ISA Bridge
7HFKQRORJLHV ,QF
:H &RQQHFW
:H &RQQHFW
Miscellaneous / General Purpose I/O
Offset 73-70 - Subsystem ID ............................................ WO
31-0 Subsystem ID and Subsystem Vendor ID
Write Only. Always reads back 0.
Contents may be read at offset 2C.
Offset 77-74 – GPIO / Chip Select Control .....................RW
31-30 Reserved
........................................ always reads 0
29
PCS1# For Internal I/O (Pin N5)
0
Disable ...................................................default
1Enable
28
PCS0# For Internal I/O (Pin L4)
0
Disable ...................................................default
1Enable
27
RTC Rx32 Remap to Rx7F Century Byte
0
Disable ...................................................default
1Enable
26
RTC Rx32 Write Protect
0
Disable ...................................................default
1Enable
25
RTC Rx0D Write Protect
0
Disable ...................................................default
1Enable
24
DMA Controller Shadow Registers
0
Disable ...................................................default
1Enable
23-22 Reserved
........................................ always reads 0
21
PCS1# Enable (Pin N5)
0
Disable ...................................................default
1Enable
20
PCS0# Enable (Pin L4)
0
Disable ...................................................default
1Enable
19
MCCS# Enable (Pin N4)
0
Disable ...................................................default
1Enable
18
GPO26 Enable (Pin K1)
0
Disable ...................................................default
1Enable
17
GPO25 Enable (Pin L1)
0
Disable ...................................................default
1Enable
16
GPO24 Enable (Pin M2)
0
Disable ...................................................default
1Enable
15
GPO23 Enable (Pin M4)
0
Disable ...................................................default
1Enable
14
GPO22 Enable (Pin M3)
0
Disable ...................................................default
1Enable
13
GPO21 Enable
0
Disable................................................... default
1Enable
12
GPO20 Enable
0
Disable................................................... default
1Enable
11
GPO19 Enable (Pin K16)
0
Disable................................................... default
1Enable
10
GPO18 Enable (Pin R2)
0
Disable................................................... default
1Enable
9
GPO17 Enable (Pin R1)
0
Disable................................................... default
1Enable
8
Decode
0
Subtractive ............................................. default
1
Positive
7APIC Enable
0
Disable................................................... default
1Enable
6
GPI12 Enable (Pin P18)
0
Disable................................................... default
1Enable
5
GPI11 Enable (Pin N17)
0
Disable................................................... default
1Enable
4
GPI10 Enable (Pin P16)
0
Disable................................................... default
1Enable
3
GPI9 Enable (Pin U19)
0
Disable................................................... default
1Enable
2
GPI8 Enable (Pin H19)
0
Disable................................................... default
1Enable
1
Internal APIC
0
Disable................................................... default
1Enable
0
GPI0/IOCHCK, GPO[7-1]/LA[23-17] Select
0
GPI0, GPO[7-1]..................................... default
1
IOCHCK, LA[23-17]
Bits 18-0 also control multi-function pin definitions. Refer to
the General Purpose Inputs and Outputs sections of the pin
descriptions for more information.



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