VT82C596B datasheet(64/96 Pages) ETC

64 / 96 page

VT82C596B

Revision 0.3 June 17, 1999

-58-

Function 3 Registers - Power Management and SMBus

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Function 3 Registers - Power Management and SMBus

This section describes the ACPI (Advanced Configuration and

Power

Interface)

Power

Management

system

the

VT82C596B which includes a System Management Bus

(SMBus) interface controller. The power management system

of the VT82C596B supports both ACPI and legacy power

management functions and is compatible with the APM v1.2

and ACPI v1.0 specifications.

PCI Configuration Space Header

Offset 1-0 - Vendor ID .......................................................RO

0-7

Vendor ID

................. (1106h = VIA Technologies)

Offset 3-2 - Device ID.........................................................RO

0-7

Device ID

................ (3050h = ACPI Power Mgmt)

Offset 5-4 - Command.......................................................RW

15-8 Reserved

........................................ always reads 0

Address Stepping ........................................fixed at 0

Reserved (parity error response) ..................fixed at 0

Reserved (VGA palette snoop) ....................fixed at 0

Memory Write and Invalidate ...................fixed at 0

Reserved (special cycle monitoring) ............fixed at 0

2Bus Master .................................................fixed at 0

Memory Space.............................................fixed at 0

I/O Space

.................................................fixed at 0

Offset 7-6 - Status ...........................................................RWC

Detected Parity Error ........................ always reads 0

Signalled System Error...................... always reads 0

Received Master Abort...................... always reads 0

Received Target Abort ...................... always reads 0

Signalled Target Abort ...................... always reads 0

10-9 DEVSEL# Timing

00 Fast

01 Medium .....................................default (fixed)

10 Slow

11 Reserved

Data Parity Detected.......................... always reads 0

Fast Back to Back Capable ............... always reads 1

6-0

Reserved

........................................ always reads 0

Offset 8 - Revision ID (nnh) .............................................. RO

7-0

Silicon Revision Code ........................... default = 20h

Offset 9 - Programming Interface (00h) .......................... RO

The value returned by this register may be changed by writing

the desired value to PCI Configuration Function 3 offset 61h.

Offset A - Sub Class Code (00h) ....................................... RO

The value returned by this register may be changed by writing

the desired value to PCI Configuration Function 3 offset 62h.

Offset B - Base Class Code (00h) ...................................... RO

The value returned by this register may be changed by writing

the desired value to PCI Configuration Function 3 offset 63h.

Offset 0D - Latency Timer ............................................... RW

7-0

Timer Value .............................................. default = 0

Offset 0E - Header Type (00h).......................................... RO

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