VT82C596B datasheet(75/96 Pages) ETC

номер детали	VT82C596B

подробное описание детали	PCI INTEGRATED PERIPHERAL CONTROLLER

PDF	96 Pages

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производитель	ETC [List of Unclassifed Manufacturers]

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VT82C596B

Revision 0.3 June 17, 1999

-69-

Function 3 Registers - Power Management and SMBus

7HFKQRORJLHV ,QF

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I/O Offset 0Ah – SMBus Slave Event ..............................RW

This register is used to enable generation of interrupt or

resume events for accesses to the host controller’s slave port.

15-0 SMBus Slave Event .................................. default = 0

This field contains data bits used to compare against

incoming data to the SMBus Slave Data Register (I/O

Offset 0Ch). When a bit in this register is set and the

corresponding bit the Slave Data register is also set,

an interrupt or resume event will be generated if the

command value matches the value in the SMBus

Slave Command register and the access was to

SMBus host address 10h.

I/O Offset 0Ch – SMBus Slave Data ................................ RO

This register is used to store data values for external SMBus

master accesses to the shadow ports or the SMBus host

controller’s slave port.

15-0 SMBus Slave Data .................................... default = 0

This field contains the data value which was

transmitted during an external SMBus master access

whose address field matched one of the slave shadow

port addresses or the SMBus host controller slave

port address of 10h.

VT82C596B датащи(PDF) 75 Page - List of Unclassifed Manufacturers