VT82C596B datasheet(74/96 Pages) ETC

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VT82C596B

Revision 0.3 June 17, 1999

-68-

Function 3 Registers - Power Management and SMBus

7HFKQRORJLHV ,QF

:H &RQQHFW

I/O Offset 08h – SMBus Slave Control............................RW

7-4

Reserved

........................................ always reads 0

SMBus Alert Enable

Disable ...................................................default

Enable generation of an interrupt or resume

event on the assertion of the SMBALERT#

signal

SMBus Shadow Port 2 Enable

Disable ...................................................default

Enable generation of an interrupt or resume

event on external SMBus master generation of

a transaction with an address that matches the

SMBus Slave Shadow Port 2 register (PCI

function 3 configuration register Rx87).

SMBus Shadow Port 1 Enable

Disable ...................................................default

Enable generation of an interrupt or resume

event on external SMBus master generation of

a transaction with an address that matches the

SMBus Slave Shadow Port 1 register (PCI

function 3 configuration register Rx86).

SlaveEnable

Disable ...................................................default

Enable generation of an interrupt or resume

event on external SMBus master generation of

a transaction with an address that matches the

SMBus host controller slave port of 10h, a

command field which matches the SMBus

Slave Command register (PCI function 3

configuration register Rx85), and a match of

one of the corresponding enabled events in the

SMBus Slave Event Register (I/O Offset 0Ah).

I/O Offset 09h – SMBus Shadow Command ................... RO

This register is used to store command values for external

SMBus master accesses to the host slave and slave shadow

ports.

7-0

Shadow Command.................................... default = 0

This field contains the command value which was

received during an external SMBus master access

whose address field matched the host slave address

(10h) or one of the slave shadow port addresses.

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