WM8595 datasheet(28/82 Pages) WOLFSON

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WM8595

Production Data

PD, Rev 4.2, January 2011

DIGITAL AUDIO DATA SAMPLING RATES

In a typical digital audio system there is one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

master clock. The WM8595 uses independent master clocks for ADC and DACs. The external

master clocks can be applied directly to the ADCMCLK, DACMCLK1 and DACMCLK2 input pins. In a

system where there are a number of possible sources for the reference clock, it is recommended that

the clock source with the lowest jitter be used for the master clock to optimise the performance of the

WM8595.

In slave clocking mode the WM8595 has a master detection circuit that automatically determines the

relationship between the master clock frequency (ADCMCLK, DACMCLK1, DACMCLK2) and the

sampling rate (ADCLRCLK, DACLRCLK1, DACLRCLK2), to within +/- 32 system clock periods. The

master clocks must be synchronised with the left/right clocks, although the device is tolerant of

phase variations or jitter on the master clocks.

The ADC supports master clock to sampling clock ratios of 256fs to 768fs and sampling rates of

32kHz to 96kHz, provided the internal signal processing of the ADC is programmed to operate at the

correct rate. The DACs support master clock to sampling clock ratios of 128fs to 1152fs and

sampling rates of 32kHz to 192kHz, provided the internal signal processing of the DACs is

programmed to operate at the correct rate.

Table 14 shows typical master clock frequencies and sampling rates supported by the WM8595

ADC. Table 15 shows typical master clock frequencies and sampling rates supported by the

WM8595 DACs.

Sampling Rate

(ADCLRCLK)

MASTER CLOCK FREQUENCY (MHZ)

256fs

384fs

512fs

768fs

32kHz

8.192

12.288

16.384

24.576

44.1kHz

11.2896

16.9344

22.5792

33.8688

48kHz

12.288

18.432

24.576

36.864

88.2kHz

22.5792

33.8688

Unavailable

96kHz

24.576

Unavailable

Table 14 ADC Master Clock Frequency Versus Sampling Rate

Sampling Rate

(DACLRCLK1

DACLRCLK2)

MASTER CLOCK FREQUENCY (MHZ)

128fs

192fs

256fs

384fs

512fs

768fs

1152fs

32kHz

Unavailable

8.192

12.288

16.384

24.576

36.864

44.1kHz

Unavailable

8.4672

11.2896

16.9344

22.5792

33.8688

Unavailable

48kHz

Unavailable

9.216

12.288

18.432

24.576

36.864

Unavailable

88.2kHz

11.2896

16.9344

22.5792

33.8688

Unavailable

96kHz

12.288

18.432

24.576

36.864

Unavailable

176.4kHz

22.5792

33.8688

Unavailable

192kHz

24.576

36.864

Unavailable

Table 15 DAC Master Clock Frequency Versus Sampling Rate

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