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WM8595 датащи(PDF) 22 Page - Wolfson Microelectronics plc |
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WM8595 датащи(HTML) 22 Page - Wolfson Microelectronics plc |
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22 / 82 page ![]() WM8595 Production Data w PD, Rev 4.2, January 2011 22 I2S MODE In I2S mode, the MSB of input data is sampled on the second rising edge of bit clock following a left/right clock transition. The MSB of output data changes on the first falling edge of bit clock following a left/right clock transition, and may be sampled on the next rising edge of bit clock. Left/right clocks are low during the left channel audio data samples and high during the right channel audio data samples. Figure 13 I2S Mode Timing LEFT JUSTIFIED (LJ) MODE In LJ mode, the MSB of the input data is sampled by the WM8595 on the first rising edge of bit clock following a left/right clock transition. The MSB of output data changes on the same falling edge of bit clock as left/right clock and may be sampled on the next rising edge of bit clock. Left/right clock is high during the left channel audio data samples and low during the right channel audio data samples. Figure 14 LJ Mode Timing |
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