WM8595 datasheet(46/82 Pages) WOLFSON

46 / 82 page

WM8595

Production Data

PD, Rev 4.2, January 2011

POP AND CLICK PERFORMANCE

The WM8595 includes a number of features designed to minimise pops and clicks in various phases

of operation including power up, power down, changing analogue paths and starting/stopping clocks.

In order to ensure optimum performance, the following sequences should be followed.

POWERUP SEQUENCE

Apply power to the WM8595 (see Power On Reset).

Set-up initial internal biases:

•

SOFT_ST=1

•

FAST_EN=1

•

POBCTRL=1

•

BUFIO_EN=1

Enable output drivers to allow the AC coupling capacitors at the output stage to be pre-

charged to VMID2C:

•

VOUTxL_EN=1

•

VOUTxR_EN=1

Enable VMID2C. Highest resistance string selected here for optimum pop reduction:

•

VMID_SEL=10

Wait until VMID2C has fully charged. The time is dependent on the capacitor values used

to AC-couple the outputs and to decouple VMID2C, and the VMID_SEL value chosen. An

approximate delay of 6xRCms can be used, where R is the VMID2C resistance (between

AVDD1 and VMID2C) and C is the decoupling capacitor on VMID2C, although this time

should be determined by the customer using the exact application configuration for best

results.

•

Insert delay

Enable the master bias and VMID2C buffer:

•

BIAS_EN=1

Switch the output drivers to use the master bias instead of the power up (fast) bias:

•

POBCTRL=0

Enable all functions (DACs, ADC, PGAs) required for use. Outputs are muted by default so

the write order is not important.

Unmute the PGAs and switch VMID2C resistance to mid setting for normal operation:

•

PGAxL_MUTE=0

•

PGAxR_MUTE=0

•

VMID_SEL=01

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