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WM8595 датащи(PDF) 42 Page - Wolfson Microelectronics plc |
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WM8595 датащи(HTML) 42 Page - Wolfson Microelectronics plc |
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42 / 82 page ![]() WM8595 Production Data w PD, Rev 4.2, January 2011 42 ADC AUDIO INTERFACE CLOCK CONFIGURATION The WM8595 ADC has an independent audio interface which can be configured to select the required signals from any of the digital audio ports. The audio interface is not restricted to take each signal from the same digital audio port, although the BCLK and LRCLK signals are selected together. The MCLK is always an input to the ADC audio interface is selected using ADCMCLK_SEL[2:0]. The BCLK and LRCLK are always selected together, and can be either an input to the ADC audio interface (when the ADC is in slave mode) or an output from the ADC audio interface (when the ADC is in master mode). BCLK and LRCLK are selected using ADCWORDCLK_SEL[2:0]. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R44 AIF_MUX5 2Ch 3:1 ADC MCLK_ SEL[2:0] 000 ADCMCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 to 111 = Reserved 6:4 ADC WORD CLK_ SEL[2:0] 000 ADC BCLK and LRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 to 110 = Reserved 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) Table 34 ADC Audio Interface Clock Configuration |
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