AD1985

Rev. A | Page 36 of 48

Jack Sense/Audio Interrupt/Status Register (Index 0x72)

Reg

Num Name

D15

D14

D13

D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x72 Jack Sense/

Audio/Status

JS

SPRD

JS1

DMX

JS0

DMX

JS

MT2

JS

MT1

JS

MT0

JS1

EQB

JS0

EQB

JS1

TMR

JS0

TMR

JS1

MD

JS0

MD

JS1

ST

JS0

ST

JS1

INT

JS0

INT

N/A

Note: All register bits are read/write except for JS0ST and JS1ST, which are read-only.

JS0INT

Indicates Pin JS0 has generated an interrupt. Remains set until the software services the JS0 interrupt; i.e., JS0 ISR (Interrupt

Service Routine) should clear this bit by writing a 0 to it.

Notes:

1) Interrupts are generated by valid state changes of JS pins.

2) Interrupt to the system is actually an OR combination of this bit and JS3INT to JS0INT.

3) The interrupt implementation path is selected by the INTS bit (Register 0x74).

4) It is also possible to generate a software system interrupt by writing a 1 to this bit.

JS1INT

Indicates Pin JS1 has generated an interrupt. Remains set until the software services the JS1 interrupt; i.e., JS1 ISR (Interrupt

Service Routine) should clear this bit by writing a 0 to it. See JS0INT description above for additional details.

JS0ST

JS0 State. This bit always reports the logic state of the JS0 pin.

Cannot be used for MIC sensing.

JS1ST

JS1 State. This bit always reports the logic state of the JS1 pin.

Cannot be used for MIC sensing.

JS0MD

JS0 Mode. This bit selects the operation mode for the JS0 pin.

0: Jack Sense Mode (Reset Default).

1: Interrupt Mode.

JS1MD

JS1 Mode: This bit selects the operation mode for the JS1 pin.

0: Jack Sense Mode (Reset Default).

1: Interrupt Mode.

JS0TMR

JS0 Timer Enable. If this bit is set to a 1, JS0 must be high for greater than 298 ms to be recognized.

JS1TMR

JS1 Timer Enable. If this bit is set to a 1, JS1 must be high for greater than 298 ms to be recognized.

JS0EQB

JS0 EQ Bypass Enable. This bit enables JS0 to control the EQ bypass.

When this bit is set to 1, JS0 = 1 will cause the EQ to be bypassed. Default is 0.

JS1EQB

JS1 EQ Bypass Enable. This bit enables JS1 to control the EQ bypass.

When this bit is set to 1, JS1 = 1 will cause the EQ to be bypassed. Default is 0.

JSMT[2:0]

JS Mute Enable Selector. These three bits select and enable the jack sense muting action (see theJack Sense Mute Select (JSMT

[2:0]) table).

JS0DMX

JS0 Down-Mix Control Enable. This bit enables JS0 to control the down-mix function. This function allows a digital mix of

6-channel audio into 2-channel audio. The mix can then be routed to the stereo LINE_OUT or HP_OUT jacks. When this bit is set

to 1, JS0 = 1 will activate the down-mix conversion.

See the DMIX description in Register 0x76. The DMIX bits select the down-mix implementation type and can also force the

function to be activated.

JS1DMX

JS1 Down-Mix Control Enable. This bit enables JS1 to control the down-mix function (see the JS0DMX description).

When this bit is set to 1, JS1 = 1 will activate the down-mix conversion.

JSSPRD

JS Spread Control Enable. This bit enables 2-channel to 6-channel audio spread function when both jack senses are active

(Logic State 1). Note that the SPRD bit can also force the spread function without being gated by the jack senses. See this bit’s

description in Register 0x76 for more details on the spread function.