AD1985

Rev. A | Page 46 of 48

OR[1:0]

Order Bits. These bits indicate the order of magnitude that the sense result Bits SR[5:0] are using. Default is 0x0.

For example, SR = 1, OR = 11; if measuring resistance, result is 1 kΩ.

SR[5:0]

Sense Result Bits. (Read-only, default 0.) These bits are used to report a vendor specific fingerprint or value. (Resistance,

impedance, reactance, etc.)

Codec ID and Clock Selection

XTL_IN

ID1

ID0

CODEC ID

CODEC CLOCKING SOURCE

GND

0

0

Secondary, ID = 3

12.288 MHz (BIT_CLK from Primary Codec)

GND

0

1

Secondary, ID = 2

12.288 MHz (BIT_CLK from Primary Codec)

GND

1

0

Secondary, ID = 1

12.288 MHz (BIT_CLK from Primary Codec)

XTAL

1

1

Primary, ID = 0

24.576 MHz (Local XTAL or External CLK into XTL_IN)

CLK Input

0

0

Primary, ID = 0

14.31818 MHZ (External into XTL_IN)

CLK Input

0

1

Primary, ID = 0

48.000 MHZ (External into XTL_IN)

CLK Input

1

X

Reserved

Reserved

Note that internally, the ID pins have weak pull-ups and are inverted.

Note also that the clock detection is done per AC ’97 Rev. 2.3 specification.