AD1985

Rev. A | Page 25 of 48

Audio Interrupt and Paging Mechanism Register (Index 0x24)

Reg Num

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3

D2

D1

D0

Default

0x24

Audio Int. and Paging

I4

I3

I2

I1

I0

X

X

X

X

X

X

X

PG3 PG2 PG1 PG0 0xXXXX

Note that this register controls the audio interrupt and register paging mechanisms.

I4

Interrupt Status (Read/Write), Default Is 0.

0: Interrupt is clear.

1: Interrupt was generated.

Interrupt event is cleared by writing a 1 to this bit. The interrupt status bit will change regardless of the setting of interrupt enable

(I0). An interrupt in the GPI in Slot 12 in the AC link will follow this bit change when interrupt enable (I0) is unmasked. If this bit is

set, one or both of I3 or I2 must be set to indicate the interrupt cause.

I[3:2]

Interrupt Cause (Read-Only), Default Is 0.

I[2] = 0: Sense status has not changed (did not cause interrupt).

I[2] = 1: Sense cycle completed or new sense information is available.

I[3] = 0: GPIO status change did not cause interrupt (default)

I[3] = 1: GPIO status change caused interrupt.

These bits will indicate the cause(s) of an interrupt. This information should be used to service the correct interrupting event(s). If

the interrupt status bit (I4) is set, one or both of these bits must be set to indicate the interrupt cause.

Hardware resets these bits back to 0 when the interrupt status bit is cleared.

I1

Sense Cycle (Read/Write), Default Is 0.

0: Sense cycle not in progress.

1: Sense cycle start.

Writing a 1 to this bit causes a sense cycle start if supported.

If a sense cycle is in progress, writing a 0 to this bit will abort the sense cycle. The data in the sense result register (0x6A, Page 1)

may or may not be valid, as determined by the IV bit in that register.

I0

Interrupt Enable (Read/Write), Default Is 0.

0: Interrupt generation is masked.

1: Interrupt generation is unmasked.

Software should not unmask the interrupt unless the AC ’97 controller ensures that no conflict is possible with modem Slot 12—

GPI functionality. AC ’97 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. In that case, software

can poll the interrupt status after initiating a sense cycle and waiting for the Sense Cycle Maximum Delay (which is defined by the

software) to determine if an interrupting event has occurred.

X

Reserved.

PG[3:0]

Page Selector (Read/Write), Default Is 0x0.

0: Vendor Specific.

0x1: Page ID 01, registers defined in AC’97, Rev. 2.3.

0x2 to 0xF: Reserved Pages.

This register is used to select a descriptor of 16-word pages between Registers 0x60 and 0x6F. A value of 0x0 is used to select

vendor specific space to maintain compatibility with AC ’97 2.2 vendor specific registers.

System software can determine implemented pages by writing the page number and reading the value back. If the value read

back does not match the value written, the page is not implemented.

All implemented pages must be in consecutive order, i.e., Page 0x2 cannot be implemented without Page 0x1.