AD1985

Rev. A | Page 18 of 48

PC Beep Register (Index 0x0A)

Reg Name

D15

D14 D13 D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 Default

0x0A PC Beep Volume PCBM X

X

PCBF7 PCBF6 PCBF5 PCBF4 PCBF3 PCBF2 PCBF1 PCBF0 PCBV3 PCBV2 PCBV1 PCBV0 X

0x8000

This register controls the level and frequency for the digital PC beep generated by the codec. Please note that PC Beep should be muted

when not in use.

PCBV[3:0]

Controls the volume of the generated signal. Each step corresponds to approximately 3 dB of attenuation. The

MSB of the register is the mute bit. When this bit is set to 1, the level for the signal is set at –∞ dB.

PCBF[7:0]

These bits are writeable, and the codec-digital PC beep generation is supported. The beep frequency generated

is the result of dividing the 48 kHz clock by 4x the number specified in PCBF[7:0], allowing tones from 47 Hz to

12 kHz. A value of 0x00 in Bits PCBF[7:0] disables internal PC beep generation. The PV bits control the volume

level of the generated signal.

The register default value is 0x8000, which corresponds to 0 dB attenuation with mute on.

PCBM

PV3 to PV0

Function

0

0000

0 dB Attenuation

0

1111

45 dB Attenuation

1

xxxx

∞ dB Attenuation

PCBF

Frequency of PC Beep

0x00

PC Beep Disabled

0x01

12 kHz

0x0C

1 kHz

0xFF

47 Hz