AD1985

Rev. A | Page 41 of 48

Advanced Jack Sense Register (Index 0x78)

Reg Num

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

Default

0x78

Advanced

Jack Sense

X

X

X

X

X

X

X

X

JS3TMR JS2TMR JS3MD JS2MD JS3ST JS2ST JS3INT JS2INT N/A

Note: All register bits are read/write except for JS2ST and JS3ST, which are read-only.

JS2INT

Indicates Pin JS2 Has Generated an Interrupt. Remains set until the software services JS2 interrupt, i.e., JS2 ISR (Interrupt

Service Routine) should clear this bit by writing a 0 to it.

Notes:

1) Interrupts are generated by valid state changes of JS pins.

2) Interrupt to the system is actually an OR combination of this bit and JS3INT to JS0INT.

3) The interrupt implementation path is selected by the INTS bit (Register 0x74).

4) It is also possible to generate a software system interrupt by writing a 1 to this bit.

JS3INT

Indicates Pin JS3 Has Generated an Interrupt. Remains set until the software services the JS3 interrupt, i.e., JS3 ISR (Interrupt

Service Routine) should clear this bit by writing a 0 to it. See the JS2INT description above for additional details.

JS2ST

JS2 State. This bit always reports the logic state of JS2 pin.

Cannot be used for MIC sensing.

JS3ST

JS3 State. This bit always reports the logic state of JS3 pin.

When the voltage reference is set to 3.7 V, the behavior of this pin is inverted to allow for MIC sensing. In this mode, an

inserted jack causes the pin to go low. All other voltage reference levels enable this pin to be used as a standard sense pin.

Only JS3 can be used for MIC sensing.

JS2MD

JS2 Mode. This bit selects the operation mode for the JS2 pin.

0: Jack Sense Mode. (Reset default.)

1: Interrupt Mode.

JS3MD

JS3 Mode. This bit selects the operation mode for the JS3 pin.

0: Jack Sense Mode. (Reset default.)

1: Interrupt Mode.

JS2TMR

JS2 Timer Enable. If this bit is set to a 1, JS2 must be high for greater than 298 ms to be recognized.

JS3TMR

JS3 Timer Enable. If this bit is set to a 1, JS3 must be asserted (see JS3ST) for greater than 298 ms to be recognized.

X

Reserved. Do not write.

Vendor ID Registers (Index 0x7C to 0x7E)

Reg Num Name D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x7C

Vendor

ID1

VIDF7 VIDF6 VIDF5 VIDF4 VIDF3 VIDF2 VIDF1 VIDF0 VIDS7 VIDS6 VIDS5 VIDS4 VIDS3 VIDS2 VIDS1 VIDS0 0x4144

VIDS[7:0]: This register is ASCII encoded to A.

VIDF[7:0]: This register is ASCII encoded to D.

Reg

Num

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x7E Vendor

ID2

VIDT7 VIDT6 VIDT5 VIDT4 VIDT3 VIDT2 VIDT1 VIDT0 VIDREV7 VIDREV6 VIDREV5 VIDREV4 VIDREV3 VIDREV2 VIDREV1 VIDREV0 0x5375

VIDT[7:0]: This register is ASCII encoded to S.

VIDREV[7:0]: This register is set to 0x75, identifying the AD1985.