AD1985

Rev. A | Page 11 of 48

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC = NO CONNECT

XTL_IN

XTL_OUT

SDATA_OUT

BIT_CLK

SDATA_IN

SYNC

RESET

JS3

LINE_OUT_R (FRONT)/SURR_R

LINE_OUT_L (FRONT)/SURR_L

JS2

LFE_OUT

CENTER_OUT

AFILT2

AFILT1

48 47 46 45 44

39 38 37

43 42 41 40

1

2

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

36

35

34

33

32

31

30

29

28

27

26

25

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AD1985

Figure 10. 48-Lead LQFP Pin Configuration

Circuit Layout Note: In normal operation, Surround and Line Out are swapped to provide headphone drive on line outputs. Therefore, Pins 35 and 36 become the

surround L/R outputs and Pins 39 and 41 become the Line Out (Front) L/R outputs with headphone drive. See Bits LOSEL and HPSEL in Register 0x76 for details.

PIN FUNCTION DESCRIPTIONS

Table 17. Digital I/O

Mnemonic

Pin No.

I/O

Description

XTL_IN

2

I

Crystal Input (24.576 MHz) or External Clock In (24.576 MHz, 14.31818 MHz, or 48.000 MHz).

XTL_OUT

3

O

Crystal Output.

SDATA_OUT

5

I

AC Link Serial Data Output. AD1985 input stream.

BIT_CLK

6

O/I

AC Link Bit Clock. 12.288 MHz serial data clock. (Input pin, for secondary mode only.)

SDATA_IN

8

O

AC Link Serial Data Input. AD1985 output stream.

SYNC

10

I

AC Link Frame Sync.

RESET

11

I

AC Link Reset. AD1985 master hardware reset.

SPDIF

48

O

SPDIF Output.

Table 18. Chip Selects/Clock Strapping

Mnemonic

Pin No.

I/O

Description

ID0

45

I

Chip Select Input 0 (Active Low).

This pin can also be used as the chain input from a secondary codec.

ID1

46

I

Chip Select Input 1 (Active Low).

Table 19. Jack Sense/EAPD

Mnemonic

Pin No.

Type

Description

EAPD

47

O

EAPD Output.

JS0

17

I

JACK SENSE 0 Input.

JS1

16

I

JACK SENSE 1 Input.

JS2

33

I

JACK SENSE 2 Input.

JS3

12

I

JACK SENSE 3 Input.