VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

internal timing

As previously explained, the SR and SV signals are required to operate the CDS. Users need to synchronize

the SR and SV clocks with the CCD signal waveform. The ADCCLK signal fine tunes the databus output in

relation to the CDS timing to achieve optimal performance (see Figure 2).

The CLAMP signal activates the clamping circuit for the input signal. The OBCLP signal activates the

optical-black calibration, and the active portion (the low pulse) of this signal must be within the optical-black

period of the CCD (see Figure 1).

ADC

The ADC employs a pipelined architecture to achieve high throughput and low-power consumption.

Fully-differential implementation and digital-error correction ensure 10-bit resolution.

The latency of the ADC data output is the default five ADCCLK cycles as shown in Figure 2. Pulling terminal 42

(OE) high puts the ADC output in high impedance.

automatic optical black calibration

In the VSP1021 device, the optical black and the system channel offset corrections are performed by an

automatic analog-feedback loop. During the optical-black-calibration interval (OBCLP = low) of each line, the

optical-black pixels plus the channel offset are sampled and compared with the desired black level specified

in the optical-black Vb setup register. The difference is then integrated and added to incoming pixel data at the

PGA input. This analog feedback loop will calibrate the PGA output to the desired black pixel level, which can

be programmed to either zero or from 20 LSBs to 35 LSBs in 1-LSB/step resolution via the serial port. The OB

calibration settles within approximately 1000 OB pixels in order to avoid line noise.

input blanking function

During the blanking period of CCD operation, large input transients may occur at the VSP1021 input, making

the ADC output unpredictable. Activating the BLKG pulse during this period will ensure a digital code of zero

at the ADC output.

user DACs

The VSP1021 device includes two user DACs that can be utilized for external analog settings. The output

voltage of each DAC can be independently set and has a range of 0 V to the supply voltage, with an 8-bit

resolution. When the user DACs are not used in a camera system, they can be put in the standby mode by

programming control bits in control register 1. The following table defines the status of the user DACs.

SOFTWARE/HARDWARE

GLOBAL STANDBY

PDD1/PDD2

DACD

STATUS OF

DAC1/DAC2

Active

0

x

Active

Active

1

x

Standby

Standby

0

0

Standby

Standby

0

1

Active

Standby

1

x

Standby

NOTE:

The hardware global standby is set by pulling down terminal 44 (STBY) of the VSP1021 device. The

software global standby is controlled by setting bit D9 (STBY) in control register 1 to 1.