VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

11

POST OFFICE BOX 655303

REGISTER DEFINITION

PGA register format (01H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default PGA gain = 00 0000 0000 (0 dB)

NOTE: The gain-code range for CCD mode is 0−767, which covers the 0-dB to 36-dB range in 0.047-dB steps. Users must employ this code range.

The gain stays at 36 dB when the code range is 768 to 1023. For the video mode, the gain code range is 256−512, which covers the 0-dB

to 12-dB range in 0.047-dB steps. Users must employ a 256−512 code range for the video mode. In video mode, the gain code 0−255

must not be used. In video mode, the gain range is from 12 dB to 24 dB for the gain code range of 513 to 767; however, the offset might

be too large for this gain range.

user DAC1 and DAC2 registers format (02H and 03H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

X

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default user DAC register value = 00 0000 0000

NOTE: The DAC1 and DAC2 codes range from 0 to 255, which covers the 0-to-AVDD output voltages at DACO1 and DACO2 output terminals

with linear correspondence.

SV/SR delay register format (04H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

X

SRL3

SRL2

SRL1

SRL0

SVL3

SVL2

SVL1

SVL0

SV/SR delay register description

BIT

NAME

DESCRIPTION

D9−D8

X

Reserved

D7−D4

SRL3−SRL0

These four bits set the internal SR delay. Set D7−D4 to 0 in video mode.

SRL3

SRL2

SRL1

SRL0

Typical internal delay

0

0

0

0

0 ns (default)

0

0

0

1

0.5 ns

:

:

1

1

1

1

7.5 ns

D3−D0

SVL3−SVL0

These four bits set the internal SV delay. Set D3−D0 to 0 in video mode.

SVL3

SVL2

SVL1

SVL0

Typical internal delay

0

0

0

0

0 ns (default)

0

0

0

1

0.5 ns

:

:

1

1

1

1

7.5 ns

Default SV/SR delay register value = 00 0000 0000