VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

12

POST OFFICE BOX 655303

REGISTER DEFINITION

optical black Vb setup register format (05H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

X

X

NOB

VB3

VB2

VB1

VB0

optical black Vb setup register description

BIT

NAME

DESCRIPTION

D9−D5

X

Reserved

D4

NOB

This bit controls the OB output.

0 = OB output is not affected by the Vb setting and it is always 0.

1 = OB output corresponds to the Vb setting (VB3−VB0).

D3−D0

VB3−VB0

VB3

VB2

VB1

VB0

OB output (when NOB = 1)

0

0

0

0

20 (default)

0

0

0

1

21

:

:

1

1

1

1

35

Default optical black Vb setup register value = 00 0000 0000

NOTE: If NOB (D4) is set to 0, VB3−VB0 (D3−D0) has no effect. The output OB is 0.

If NOB is set to 1, the output OB is defined by VB3−VB0, and ranges from 20 LSB to 35 LSB.

control register 2 format (06H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ADL3

ADL2

ADL1

ADL0

X

X

X

GNDV

MOD

X

control register 2 description

BIT

NAME

DESCRIPTION

D9−D6

ADL3−ADL0

These four bits set the internal ADCCLK delay.

ADL3

ADL2

ADL1

ADL0

Typical internal delay

0

0

0

0

0 ns (default)

0

0

0

1

0.5 ns

:

:

1

1

1

1

7.5 ns

D5−D3

X

Reserved

D2

GNDV

This bit defines whether to short the video terminal (PIN) to ground (VSS) internally.

0 = No short (default)

1 = Short the video terminal to ground (VSS)

D1

MOD

This bit defines the mode of the input.

0 = CCD mode (default)

1 = Video mode

D0

X

Reserved. Always program this bit to 0.

Default register value = 00 0000 0000