VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

10

POST OFFICE BOX 655303

REGISTER DEFINITION

serial input data format

DI15

DI14

DI13

DI12

DI11

DI10

DI9

DI8

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

X

X

A3

A2

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

A3

A2

A1

A0

D9−D0

0

0

0

0

Control register 1

10-bit data to be written into the selected register

0

0

0

1

PGA gain register

0

0

1

0

User DAC1 register

0

0

1

1

User DAC2 register

0

1

0

0

SR/SV delay

0

1

0

1

Optical-black Vb setup register

0

1

1

0

Control register 2

control register 1 format (00H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

STBY

PDD2

PDD1

DACD

X

X

X

PSVR

X

RTSY

control register 1 description

BIT

NAME

DESCRIPTION

D9

STBY

Device global power-down control:

1 = Standby

0 = Active (default)

D8

PDD2

Power down the user DAC2:

0 = Active (default)

1 = Standby

D7

PDD1

Power down the user DAC1:

0 = Active (default)

1 = Standby

D6

DACD

Sustain the user DACs in global standby

0 = User DACs are in standby during global standby (default)

1 = User DACs are not in standby during global standby

D5

X

Reserved

D4

X

Reserved

D3

X

Reserved

D2

PSVR

This bit sets the polarity of the SV/SR.

0 = SV and SR are active low (default)

1 = SV and SR are active high

D1

X

Reserved

D0

RTSY

Writing 1 to this bit resets the entire system to the default settings (active high).

Default = 00 0000 0000