VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

5

POST OFFICE BOX 655303

AVDD = DVDD = 3 V, ADCCLK = 25 MHz (unless otherwise noted)

total device

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Device power consumption

AVDD = DVDD = 3 V

105

mW

Device power consumption

AVDD = DVDD = 2.7 V

95

mW

Power consumption in power-down mode

1

mW

Full-scale input span

1

Vp-p

Full-channel nonlinearity

0.5

1

LSB

No missing code

Assured

analog-to-digital converter (ADC)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC resolution

10 (CCD)

Bits

ADC resolution

8 (Video)

Bits

INL

Integral nonlinearity

AVDD=DVDD= 2.7 V to 3.3 V

±1.2

LSB

DNL

Differential nonlinearity

AVDD=DVDD= 2.7 V to 3.3 V

±0.5

±0.99

LSB

Conversion rate

25 (CCD)

MHz

Conversion rate

28 (Video)

MHz

ADC output latency

5

CLK

cycles

SNR

Input-referred signal-to-noise ratio

0-dB gain

65

dB

SNR

Input-referred signal-to-noise ratio

36-dB gain

78

dB

correlated double sampler(CDS) and programmable-gain amplifier (PGA)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CDS and PGA sample rate

25 (CCD)

MHz

CDS and PGA sample rate

28 (Video)

MHz

CDS full-scale input span

Single-ended input

1

V

Input capacitance of CDS

4

pF

Minimum PGA gain

0

dB

Maximum PGA gain

CCD

36

dB

Maximum PGA gain

Video

12

dB

PGA gain resolution

0.047

dB

PGA programming-code resolution

10-bit monotonic gain control

10

Bits

user digital-to-analog converter (DAC)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DAC resolution

8

Bits

INL

Integral nonlinearity

±1

LSB

DNL

Differential nonlinearity

±0.5

LSB

Output voltage range

0

AVDD

V

Output settling time

10-pF external load, settle to 1 mV

4

µs