VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

6

POST OFFICE BOX 655303

AVDD = DVDD = 3 V, ADCCLK = 25 MHz (unless otherwise noted) (continued)

reference voltages

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal bandgap-voltage reference

1.43

1.50

1.58

V

Temperature coefficient

100

ppm/

°C

Voltage-reference noise

0.5

LSB

ADC Ref+

Externally decoupled

2

V

ADC Ref−

Externally decoupled

1

V

digital specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Logic Inputs

IIH

High-level input current

DVDD = 3 V

−10

10

A

IIL

Low-level input current

DVDD = 3 V

−10

10

µA

Ci

Input capacitance

5

pF

Logic Outputs

VOH

High-level output voltage

IOH = 50 µA,

DIVDD = 3 V

DIVDD−0.4

V

VOL

Low-level output voltage

IOL = 50 µA,

DIVDD = 3 V

0.4

V

IOZ

High-impedance-state output current

±10

µA

CO

Output capacitance

5

pF

key timing requirements

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tSRW

SR pulse width

Measured at 50% of pulse

height, recommend to use 1/4

of ADCCLK cycle

10

ns

tSVW

SV pulse width

Measured at 50% of pulse

height, recommend to use 1/4

of ADCCLK cycle

10

ns

tSRD

Delay between the SR rising edge (SR active low) and

the actual sampling instant

Measured at 50% of pulse

height

5

ns

tSVD

Delay between the SV falling edge (SV active low) and

the actual instant of sampling the video signal

Measured at 50% of pulse

height

8

ns

tADC_SV

Delay between the SV falling edge (SV active low) and

the ADCCLK rising edge

Measured at 50% of pulse

height

10

ns

tOD

ADCCLK-to-output data delay

Measured at 50% of pulse

height

6

ns

Maximum internal delay for SR, SV, and ADCCLK timing

signals

With 16 programmable delay

steps

7.5

ns

SR, SV, and ADCCLK delay resolution

0.5

ns

tCSF

CS falling edge to SCLK rising edge when SCKP = 1, or

CS falling edge to SCLK falling edge when SCKP = 0

Measured at 50% of pulse

height

0

ns

tCSR

SCLK falling edge to CS rising edge when SCKP = 1, or

SCLK falling edge to CS falling edge when SCKP = 0

Measured at 50% of pulse

height

5

ns