TMP320C2811PBKA datasheet(21/147 Pages) TI

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Introduction

June 2004

SPRS257

Table 2−2. Signal Descriptions† (Continued)

NAME

DESCRIPTION

PU/PD§

I/O/Z‡

PIN NO.

NAME

DESCRIPTION

PU/PD§

I/O/Z‡

128-PIN

PBK

176-PIN

PGF

179-PIN

GHH

AND

ZHH

JTAG

TRST

B12

135

JTAG test reset with internal pulldown. TRST, when driven

high, gives the scan system control of the operations of the

device. If this signal is not connected or driven low, the device

operates in its functional mode, and the test reset signals are

ignored.

NOTE: Do not use pullup resistors on TRST; it has an internal

pulldown device. In a low-noise environment, TRST can be

left floating. In a high-noise environment, an additional

pulldown resistor may be needed. The value of this resistor

should be based on drive strength of the debugger pods

applicable to the design. A 2.2-kΩ resistor generally offers

adequate protection. Since this is application-specific, it is

recommended that each target board is validated for proper

operation of the debugger and the application.

TCK

A12

136

JTAG test clock with internal pullup

TMS

D13

126

JTAG test-mode select (TMS) with internal pullup. This serial

control input is clocked into the TAP controller on the rising

edge of TCK.

TDI

C13

131

JTAG test data input (TDI) with internal pullup. TDI is clocked

into the selected register (instruction or data) on a rising edge

of TCK.

TDO

D12

127

O/Z

−

JTAG scan out, test data output (TDO). The contents of the

selected register (instruction or data) is shifted out of TDO on

the falling edge of TCK.

EMU0

D11

137

100

I/O/Z

Emulator pin 0. When TRST is driven high, this pin is used

as an interrupt to or from the emulator system and is

defined as input/output through the JTAG scan.

EMU1

146

105

I/O/Z

Emulator pin 1. When TRST is driven high, this pin is used

as an interrupt to or from the emulator system and is

defined as input/output through the JTAG scan.

ADC ANALOG INPUT SIGNALS

ADCINA7

167

119

ADCINA6

168

120

ADCINA5

169

121

ADCINA4

170

122

8-Channel analog inputs for Sample-and-Hold A. The ADC

pins should not be driven before V

and V

ADCINA3

171

123

pins should not be driven before VDDA1, VDDA2, and VDDAIO

pins have been fully powered up.

ADCINA2

172

124

pins have been fully powered up.

ADCINA1

173

125

ADCINA0

174

126

† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡ I = Input, O = Output, Z = High impedance

§ PU = pin has internal pullup; PD = pin has internal pulldown

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