TMP320C2811PBKA datasheet(69/147 Pages) TI

69 / 147 page

Peripherals

June 2004

SPRS257

Table 4−7 provides a summary of the McBSP registers.

Table 4−7. McBSP Register Summary

NAME

ADDRESS

0x00 78xxh

TYPE

(R/W)

RESET VALUE

(HEX)

DESCRIPTION

DATA REGISTERS, RECEIVE, TRANSMIT†

−

0x0000

McBSP Receive Buffer Register

−

0x0000

McBSP Receive Shift Register

−

0x0000

McBSP Transmit Shift Register

DRR2

0x0000

McBSP Data Receive Register 2

− Read First if the word size is greater than 16 bits,

else ignore DRR2

DRR1

0x0000

McBSP Data Receive Register 1

− Read Second if the word size is greater than 16 bits,

else read DRR1 only

DXR2

0x0000

McBSP Data Transmit Register 2

− Write First if the word size is greater than 16 bits,

else ignore DXR2

DXR1

0x0000

McBSP Data Transmit Register 1

− Write Second if the word size is greater than 16 bits,

else write to DXR1 only

McBSP CONTROL REGISTERS

SPCR2

R/W

0x0000

McBSP Serial Port Control Register 2

SPCR1

R/W

0x0000

McBSP Serial Port Control Register 1

RCR2

R/W

0x0000

McBSP Receive Control Register 2

RCR1

R/W

0x0000

McBSP Receive Control Register 1

XCR2

R/W

0x0000

McBSP Transmit Control Register 2

XCR1

R/W

0x0000

McBSP Transmit Control Register 1

SRGR2

R/W

0x0000

McBSP Sample Rate Generator Register 2

SRGR1

R/W

0x0000

McBSP Sample Rate Generator Register 1

MULTICHANNEL CONTROL REGISTERS

MCR2

R/W

0x0000

McBSP Multichannel Register 2

MCR1

R/W

0x0000

McBSP Multichannel Register 1

RCERA

R/W

0x0000

McBSP Receive Channel Enable Register Partition A

RCERB

R/W

0x0000

McBSP Receive Channel Enable Register Partition B

XCERA

R/W

0x0000

McBSP Transmit Channel Enable Register Partition A

XCERB

R/W

0x0000

McBSP Transmit Channel Enable Register Partition B

PCR1

R/W

0x0000

McBSP Pin Control Register

RCERC

R/W

0x0000

McBSP Receive Channel Enable Register Partition C

RCERD

R/W

0x0000

McBSP Receive Channel Enable Register Partition D

XCERC

R/W

0x0000

McBSP Transmit Channel Enable Register Partition C

XCERD

R/W

0x0000

McBSP Transmit Channel Enable Register Partition D

† DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.

‡ FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.

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