TMP320C2811PBKA datasheet(31/147 Pages) TI

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Functional Overview

June 2004

SPRS257

Table 3−1. Wait States

AREA

WAIT-STATES

COMMENTS

M0 and M1 SARAMs

0-wait

Fixed

Peripheral Frame 0

0-wait

Fixed

Peripheral Frame 1

0-wait (writes)

2-wait (reads)

Fixed

Peripheral Frame 2

0-wait (writes)

2-wait (reads)

Fixed

L0, L1, L2, and L3 SARAMs

0-wait

H0 SARAM

0-wait

Fixed

Boot-ROM

1-wait

Fixed

XINTF

Programmable,

1-wait minimum

Programmed via the XINTF registers.

Cycles can be extended by external memory or peripheral.

0-wait operation is not possible.

3.2

Brief Descriptions

3.2.1

C28x CPU

The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source

code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant

software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop

not only their system control software in a high-level language, but also enables math algorithms to be

developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically

are handled by microcontroller devices. This efficiency removes the need for a second processor in many

systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x

to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive

floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical

registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency.

The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables

the C28x to execute at high speeds without resorting to expensive high-speed memories. Special

branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional

operations further improve performance.

3.2.2

Memory Bus (Harvard Bus Architecture)

As with many DSP type devices, multiple busses are used to move data between the memories and

peripherals and the CPU. The R28x memory bus architecture contains a program read bus, data read bus

and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and

write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single

cycle 32-bit operations. The multiple-bus architecture, commonly termed “Harvard Bus”, enables the R28x

to fetch an instruction, read a data value, and write a data value in a single cycle. All peripherals and memories

attached to the memory bus prioritize memory accesses.

C28x and TMS320C2000 are trademarks of Texas Instruments.

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