MEC1322 datasheet(147/456 Pages) MICROCHIP

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DS00001719D-page 147

MEC1322

11.9

Description

11.9.1

BLOCK DIAGRAM

11.10 EC-to-Host Keyboard Communication

The EC can write to the EC_HOST Data / AUX Data Register by writing to the HOST2EC Data Register at EC-Only

offset 0h or the EC AUX Data Register at EC-Only offset Ch. A write to either of these addresses automatically sets bit

0 (OBF) in the Status register. A write to the HOST2EC Data Register may also set PCOBF. A write to the EC AUX Data

11.10.1

PCOBF DESCRIPTION

If enabled by the bit OBFEN, the bit PCOBF is gated onto KIRQ. The KIRQ signal is a system interrupt which signifies

that the EC has written to the HOST2EC Data Register (EC-Only offset 0h). On power-up, PCOBF is reset to 0. PCOBF

will normally reflect the status of writes to HOST2EC register, if PCOBFEN is “0”. PCOBF is cleared by hardware on a

HOST read of the EC_HOST Data / AUX Data Register.

KIRQ is normally selected as IRQ1 for keyboard support.

Additional flexibility has been added which allows firmware to directly control the PCOBF output signal, independent of

data transfers to the host-interface data output register. This feature allows the MEC1322 to be operated via the host

“polled” mode. Firmware control is active when PCOBFEN is ‘1’. Firmware sets PCOBF high by writing a “1” to the

PCOBF field of the PCOBF Register. Firmware must also clear PCOBF by writing a “0” to the PCOBF field.

The PCOBF register is also readable; the value read back on bit 0 of the register always reflects the present value of

the PCOBF output. If PCOBFEN = 1, then this value reflects the output of the firmware latch in the PCOBF Register. If

PCOBFEN = 0, then the value read back reflects the in-process status of write cycles to the HOST2EC Data Register

(i.e., if the value read back is high, the host interface output data register has just been written to). If OBFEN=0, then

KIRQ is driven inactive (low).

FIGURE 11-2:

BLOCK DIAGRAM OF 8042 Emulated Keyboard Controller

SPB offset =100h

Read Data or CMD

AUXH = 1 Bit [5] is AUXOBF

AUXH = 0 Bit [5] is UD

IBF SET on Host Write to LPC I/O

Index =00h or 04h

IBF Cleared on EC Read to SPB

Offset = 00h

OBF SET on EC Write to

SPB offset = 100h or 10Ch

OBF Cleared by Read 0f

LPC I/O Index 00h

4 PCOBFEN = 1 PCOBF is contents of Bit 0 SPB offset = 114h

PCOBFEN = 0 PCBOBF is set on EC Write of SPB offset = 100 h

PCOBF is cleared on Host Read of LPC I/O index = 00h

C/D

AUXOBF / UD

OBF3

IBF2

UD1

HOST_EC Data register

Status Register

Keyboard Control Register

LPC I/O Index =00

Write Data

LPC I/O read index =04h

SPB offset =104h

Access

Host

Access

1 This bit is reset by

LPCRESET and VTR_POR

RES

PCOBF Register

FF_0514

AUXH

OBFEN

SAEN

PCOBFEN

EC_HOST Data Register

SPB offset =10Ch

Write Aux Data

SPB offset =100h

Write Data

FF_0508

PCOBF4

LPC I/O Index =04

Write CMD

LPC I/O Index =00

Read Data or AUX Data

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