MEC1322 datasheet(229/456 Pages) MICROCHIP

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DS00001719D-page 229

MEC1322

18.6

Host Interface

The registers defined for the Hibernation Timer are accessible by the various hosts as indicated in Section 18.10, "EC-

Only Registers".

18.7

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

18.7.1

POWER DOMAINS

18.7.2

CLOCK INPUTS

18.7.3

RESETS

18.8

Interrupts

This section defines the interrupt Interface signals routed to the chip interrupt aggregator.

Each instance of the Hibernation Timer in the MEC1322 can be used to generate interrupts and wake-up events when

the timer decrements to zero. The Hibernation Timer interrupt is are routed to the HTIMER bit in the GIRQ17 Source

18.9

Low Power Modes

The Hibernation Timer may be put into a low power state by the chip Power, Clocks, and Reset (PCR) circuitry.

The timer operates off of the 32KHz_Clk, and therefore will operate normally when 48 MHz Ring Oscillator is stopped.

The sleep enable inputs have no effect on the Hibernation Timer and the clock required outputs are only asserted during

18.10 EC-Only Registers

The registers listed in the EC-Only Register Summary table are for a single instance of the Hibernation Timer. The

addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the

EC-Only Register Base Address Table.

TABLE 18-1:

POWER SOURCES

Name

Description

VCC1

The timer control logic and registers are all implemented on this single

power domain.

TABLE 18-2:

CLOCK INPUTS

Name

Description

32KHz_Clk

This is the clock source to the timer logic. The Pre-scaler may be used

to adjust the minimum resolution per bit of the counter.

if the main oscillator is stopped then an external 32.768kHz clock source

must be active for the Hibernation Timer to continue to operate.

TABLE 18-3:

RESET SIGNALS

Name

Description

VCC1_RESET

This reset signal, which is an input to this block, resets all the logic and

registers to their initial default state.

TABLE 18-4:

INTERRUPT INTERFACE SIGNAL DESCRIPTION TABLE

Name

Direction

Description

HTIMER

Output

Signal indicating that the timer is enabled and decrements to 0. This

signal is used to generate an Hibernation Timer interrupt event.

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