KAF−8300

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7

Physical Description

Pin Description and Device Orientation

Figure 6. Pinout Diagram

SUB

OG

RG

RD

RD

VSS

VOUT

VDD

SUB

H1L

N/C

SUB

H1

H1

H2

H2

N/C

LODT

V1

V2

V2

SUB

N/C

V2

V2

V1

V1

SUB

N/C

N/C

LODB

1

16

32

17

Pin 1 Indicator

V1

231

330

429

528

627

726

825

924

10

23

11

22

12

21

13

20

14

19

15

18

Table 4. PIN DESCRIPTION

Pin

Name

Description

1

SUB

Substrate

2

OG

Output Gate

3

RG

Reset Gate

4

RD

Reset Drain Bias

5

RD

Reset Drain Bias

6

VSS

Output Amplifier Return

7

VOUT

Output

8

VDD

Output Amplifier Supply

9

SUB

Substrate

10

Horizontal Phase 1, Last Gate

11

N/C

No Connection

12

SUB

Substrate

13

H1

Horizontal Phase 1

14

H1

Horizontal Phase 1

15

H2

Horizontal Phase 2

16

H2

Horizontal Phase 2

Pin

Name

Description

17

LODB

Lateral Overflow Drain Bottom

18

N/C

No Connection

19

N/C

No Connection

20

SUB

Substrate

21

V1

Vertical Phase 1

22

V1

Vertical Phase 1

23

V2

Vertical Phase 2

24

V2

Vertical Phase 2

25

N/C

No Connection

26

SUB

Substrate

27

V2

Vertical Phase 2

28

V2

Vertical Phase 2

29

V1

Vertical Phase 1

30

V1

Vertical Phase 1

31

LODT

Lateral Overflow Drain Top

32

N/C

No Connection

1. Wherever possible, all N/C pins (11, 18, 19, 25, 32) should be connected to GND (0 V).