RF63 datasheet(13/91 Pages) ETC2

13 / 91 page

ADVANCED COMMUNICATIONS & SENSING

Page 13 of 91

RF63

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Reg_ana

1.0 V

Biasing analog

blocks

Reg_dig

1.0 V

Biasing digital

blocks

Reg_VCO

0.85 V

Biasing :

-VCO circuit

-Ext. VCO

tank

Reg_PA

1.80 V

Biasing :

-PA Driver

-PA choke

(ext)

Vbat

1ųF

Y5V

VDD

— Pin 26

2.1

— 3.6V

External Supply

Reg_top

1.4 V

Biasing :

-SPI

-Config. Registers

-POR

VR_1V

Pin 27

VR_DIG

Pin 28

VR_VCO

Pin 3

VR_PA

Pin 29

ųF

Y5V

220nF

X7R

100nF

X7R

47nF

X7R

Figure 4: Power Supply Breakdown

To ensure correct operation of the regulator circuit, the decoupling capacitor connection shown in Figure 4 is

required. These decoupling components are recommended for any design.

3.2. Frequency Synthesis Description

The frequency synthesizer of the RF63 is a fully integrated integer-N type PLL. The PLL circuit requires only five

external components for the PLL loop filter and the VCO tank circuit.

3.2.1. Reference Oscillator

The RF63 embeds a crystal oscillator, which provides the reference frequency for the PLL. The recommended

crystal specification is given in section 7.1.

3.2.2. CLKOUT Output

The reference frequency, or a sub-multiple of it, can be provided on CLKOUT (pin 19) by activating the bit

OSCParam_Clkout_on. The division ratio is programmed through bits OSCParam_Clkout_freq. The two

applications of the CLKOUT output are:

•

To provide a clock output for a companion uC, thus saving the cost of an additional oscillator. CLKOUT can be

made available in any operation mode, except Sleep mode, and is automatically enabled at power-up.

•

To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software

trimming of the initial crystal tolerance.

Note: To minimize the current consumption of the RF63, ensure that the CLKOUT signal is disabled when unused.

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