STC5455 datasheet(6/56 Pages) CONNOR-WINFIELD

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TM121

Rev:P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Data sheet

Preliminary

STC5455 Pin Description

CLK1, REF4 and REF5 are LVPECL/LVDS. Other I/O is LVCMOS.

Table 1: Pin Description

Pin Name

Pin #

I/O

Description

AVCC

4,14

3.3V analog power input

AGND

3,15

Analog ground

VCC

8, 9, 12,

22, 32,

36, 38,

39, 45,

46, 54,

3.3V digital power input

GND

1, 7, 10,

11, 21,

31, 40,

53, 58

Digital ground

TRST

JTAG boundary scan reset, active low

TCK

JTAG boundary scan clock

TMS

JTAG boundary scan mode selection

TDI

JTAG boundary scan data input

TDO

JTAG boundary scan data output

RST

Active low to reset the chip

MCLK

Master clock input (TCXO or OCXO)

EVENT_INTR

Event interrupt

EX_SYNC1

External Frame Sync input 1

EX_SYNC2

External Frame Sync input 2

EX_SYNC3

External Frame Sync input 3

REF1

Reference input 1

REF2

Reference input 2

REF3

Reference input 3

REF4_P

Differential reference input 4 (LVPECL/LVDS)

REF4_N

Differential reference input 4 (LVPECL/LVDS)

REF5_P

Differential reference input 5 (LVPECL/LVDS)

REF5_N

Differential reference input 5 (LVPECL/LVDS)

CLK1_P

Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1

LVPECL or LVDS

CLK1_N

Clock output CLK1 negative, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1

LVPECL or LVDS

CLK2

Clock output CLK2 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G2; 2.048MHz

from Synthesizer GT4 (T4); Frame8K or Frame2K from Synthesizer F. LVCMOS.

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