STC5455 datasheet(18/56 Pages) CONNOR-WINFIELD

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Page 18 of 56 TM121 Rev: P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Functional Specification

Data sheet

Preliminary

tory. This history is accumulated by a built in program-

mable short-term history accumulator consecutively,

which indicates the latest updated fractional fre-

quency offset of the synchronous clock output of each

timing generator. The user can read the short-term

history from register Short Term Accu History.

Holdover Mode

Holdover mode is used when none of reference

inputs is available and the holdover history has been

built. In this condition, the frequency offset of the

clock output is maintained closely to previous value

generated when the selected reference input was

valid. User can select either device holdover history

or user specified holdover history at the register Con-

trol Mode in holdover mode.

PLL Event In

The STC5455 provides direct communication with the

PLL’s timing generator by writing to the register PLL

Event In. Following events can be triggered:

- Relock. PLL starts a relock process if this event is trig-

gered. In frame phase align mode, PLL relocks to the ref-

erence input and the frame edge is re-selected as well.

In phase arbitrary mode, PLL relocks to the reference

input and restart the phase rebuild process.

Frequency and Phase Transients

Severe frequency and phase transients of the clock

output will cause lost of lock or buffer overflow/under-

flow on downstream circuit. By providing programma-

ble maximum slew rate and phase rebuild function,

both frequency and phase transient of the STC5455’s

clock output is controlled to minimize the impact on

downstream circuits.

Frequency Transients

The STC5455 smoothly control the frequency tran-

sient on the clock output. During reference input

switching or operation mode switching (etc., enter fre-

erun or holdover mode), if the clock output prior to

switching has different frequency offset than the

desired clock output, it smoothly approach to desired

frequency offset with a maximum acceleration/decel-

eration rate by writing to the register History Ramp.

The maximum slew rate can be programmed as 1.0,

1.5, 2.0 ppm/second. With a limited acceleration/

deceleration rate, the pull-in process may last longer.

However, it will minimize the frequency transient

impact to the downstream clock and ensure meeting

components frequency impact tolerance.

Phase Transients

The STC5455 minimize the variation of the phase

transient on the clock output when a phase hit occurs

on the selected reference input. The overshoot in the

clock output’s phase transient response will be a

small amount under 2%.

During reference input switching or recovering from

LOS/LOL condition, the phase transient may also

occurred on the clock output. The STC5455 can mini-

mize it with a phase rebuild function. In synchronized

mode, the phase relationship between the reference

input and the clock output can be programmed to

phase arbitrary or frame phase align at the register

Frame Phase Align. If phase arbitrary is selected, a

phase rebuild function is performed before locking to

the new/recovered reference input. Hit-less switching

is achieved with this function and the phase hit to

downstream circuits is eliminated. If frame phase

align is selected, the reference input is in frame

phase alignment with the clock output. Only T0 timing

generator supports frame phase alignment.

History of Fractional Frequency

Offset

The STC5455 monitors and tracks the fractional fre-

quency offset between the clock output and MCLK.

The history data of the frequency offset is used by

clock synthesizers to generate desire outputs while

the timing generator is pending for reference input

availability. Two weighted 3rd order low-pass filter are

used internally as two history accumulators: the short

term history accumulator and the long term history

accumulator. A mature long term history is stored and

further updated as device holdover history. It is used

when the STC5455 operates in holdover mode. In

addition, the STC5455 allows user to program an

user specified history as needed of the application.

Short-Term History

Short-term history is an average frequency offset

between the clock output and MCLK which is filtered

internally using a weighted 3rd order low-pass filter

with the small time constant. The -3dB filter response

point can be programmed from 0.16Hz to 1.3Hz by

writing to the register History Ramp register. Short-

term

history

can

read

from

the

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