STC5455 datasheet(44/56 Pages) CONNOR-WINFIELD

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TM121

Rev:P1.3

Date: October 24, 2011

STC5455

Synchronous Clock for SETS

Data sheet

Preliminary

Default value: 0

Frame8K_Sel, 0x59 (R/W)

Frame2K_Sel, 0x5A (R/W)

Selects duty cycle of the Frame8K and Frame2K generated from synthesizer F and determine frame edge is

rising or falling. Set Bit5~0 to 0 to put CLK8K/CLK2K into tri-state and put Frame8K/Frame2K of synthesizer F

to ground.

Default value: 0 (Tri-state/ground, not inverted)

Ref_Acceptable_Freq, 0x5B (R/W)

Enable frequency auto detect function or set integer N for the manual acceptable reference frequency for indi-

vidual reference input.

Setting this register to 0 is to enable frequency auto detection for reference input which is selected at the regis-

ter Ref_Index_Selector. The auto-detect acceptable reference input frequencies are shown in Table 3.

Select the integer N for the manually acceptable reference frequency at Nx8kHz (N is integer from 1 to 32767)

for REF1 ~ REF5. Which of reference inputs is selected for the manually acceptable reference is depending on

Synthesizer G2 (T0)

Reserved

Synthesizer F Frame8K

Synthesizer F Frame2K

CLK2 tie to ground

Synthesizer GT4 (T4)

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x59

Not used

Invert

Duty Cycle Select for Frame8K or put CLK8K into tri-state

0x5A

Not used

Invert

Duty Cycle Select for Frame2K or put CLK2K into tri-state

Bit 5 ~ 0

Duty Cycle Select

Put CLK8K/CLK2K into tri-state and put Frame8K/Frame2K to ground

1~62

Pulse width 1 to 62 cycle of 155.52MHz

50% duty cycle

Bits 6

Invert

Not inverted (frame on rising edge)

Inverted (frame on falling edge)

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x5B

Lower 8 bits of integer N Select

0x5C

Not used

Higher 7 bits of integer N Select

Frame_Mux

(Bit1~Bit0)

Bits 1 ~ 0

CLK2 Synthesizer Select

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