IR36021 datasheet(14/41 Pages) IRF

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IR36021

DIGITAL POL BUCK CONTROLLER with I2C AND PMBus

Interface

February 27, 2013 | Rev 3.5

GENERAL DESCRIPTION

The IR36021 is a flexible, dual‐loop (dual‐channel), digital

multiphase PWM buck controller optimized to convert a

12V input supply to a voltage below 2.445V (for VCC>3.1V).

It is easily configurable for 1‐2 phase operation on Loop #1

and 0‐1 phase operation on Loop #2.

The unique partitioning of analog and digital circuits within

the IR36021 provides the user with easy configuration

capability while maintaining the required accuracy and

performance.

Access

on‐chip

Multiple

Time

Programming memory (MTP) to store the IR36021

configuration parameters enables power supply designers

to optimize their designs without changing external

components.

The IR36021 controls two independent output voltages.

Each voltage is controlled in an identical fashion, so that

the user can configure and optimize each control loop

individually. Unless otherwise described, the following

functions are performed on the IR36021 on each control

loop independently.

DIGITAL CONTROLLER & PWM

A linear Proportional‐Integral‐Derivative (PID) digital

controller provides the loop compensation for system

regulation. The digitized error voltage from the high‐speed

voltage error ADC is processed by the digital compensator.

The digital PWM generator uses the outputs of the PID and

the phase current balance control signals to determine the

pulse width for each phase on each loop. The PWM

generator has enough resolution to ensure that there are

no limit cycles. The compensator coefficients are user

configurable to enable optimized system response.

The compensation algorithm uses a PID with two

additional programmable poles. This provides the digital

equivalent of a Type III analog compensator.

ADAPTIVE TRANSIENT ALGORITHM (ATA)

Dynamic load step‐up and load step‐down transients

require fast system response to maintain the output

voltage within specification limits. This is achieved by a

unique adaptive non‐linear digital transient control loop

based on a proprietary algorithm.

MULTIPLE TIME PROGRAMMING MEMORY

The multiple time programming memory (MTP) stores the

device configuration. At power‐up, MTP contents are

transferred to operating registers for access during device

operation. MTP allows customization during both design

and high‐volume manufacturing. MTP integrity is verified

by cyclic redundancy code (CRC) checking on each power

up. The controller will not start in the event of a CRC error.

The IR36021 offers up to 9 writes to configure basic

device parameters such as frequency fault operating

characteristics, and boot voltage. This represents a

significant size and component saving compared to

traditional analog methods. The following pseudo‐code

illustrates how to write the MTP:

# write data

Set MTP Command Register = WRITE,

Line Pointer = An unused line

Poll MTP Command Register until Operation = IDLE.

# verify data was written correctly

Issue a READ Command; then poll OTP Operation Register

till Operation = IDLE

Verify that the Read Succeeded

INTERNAL OSCILLATOR

The IR36021 has a single 96MHz internal oscillator that

generates all the internal system clock frequencies

required for proper device function. The single internal

oscillator is also used to set the switching frequency on

each loop. The switching frequency for the two loops can

be set to different values independently. Therefore, the

two channels switch asynchronously.

HIGH‐PRECISION VOLTAGE REFERENCE

The internal high‐precision voltage reference supplies the

required reference voltages to the DACs, ADCs and other

analog circuits. This factory trimmed reference is

guaranteed over

temperature

and

manufacturing

variations.

HIGH PRECISION CURRENT REFERENCE

An on‐chip precision current reference is derived using

an off‐chip precision resistor connected to the RRES pin of

the IR36021. RRES must be a 7.5kΩ, 1% tolerance resistor,

placed very close to the controller pin to minimize

parasitics.

VOLTAGE SENSE

An error voltage is generated from the difference between

the target voltage and load‐line (if implemented), and the

differential, remotely sensed, output voltage. For each

loop, the error voltage is digitized by a high‐speed, high‐

PWM1

PWM2

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