IR36021 datasheet(23/41 Pages) IRF

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IR36021

DIGITAL POL BUCK CONTROLLER with I2C AND PMBus

Interface

February 27, 2013 | Rev 3.5

Even though the loadline is disabled digitally, the resistors

and loadline and scaling registers should be set such that

the load line is at least 3 times the value of low ohmic DCR

inductors (<0.5mΩ) or 1 times the DCR value for high

ohmic inductors (>0.5mΩ), e.g. if the inductor(s) DCR is

0.3mΩ, a notional 0.9 mΩ load line should be set. For

accurate current measurement and OCP threshold with the

loadline disabled, the output current gain and scaling

registers must be set to the same value as the loadline set

with the external resistor network. With loadline disabled,

the thermistor and Css capacitor must still be installed to

insure accuracy of the current measurement.

DIGITAL FEEDBACK LOOP & PWM

The IR36021 uses a digital feedback loop to minimize the

requirement for output decoupling and maintain a tightly

regulated output voltage. The error between the target

and the output voltage is digitized. This error voltage is

then passed through a low pass filter to smooth ripple

and then passed through a PID (Proportional Integral

Derivative) compensator followed by an additional single

pole filter. The loop compensation parameters Kp

(proportional coefficient), KI (integral coefficient), and KD

(derivative coefficient) and low‐pass filter pole locations

are user configurable to optimize the VR design for the

chosen external components.

The IR36021 significantly reduces design time because

the loop coefficients need to be calculated only once.

Simply enable any number of phases (1 or 2 for loop1) and

design the compensation coefficients. The IR36021 will

intelligently scale the coefficients and low‐pass filters

automatically as one phase is dynamically added and

dropped to maintain optimum stability. In other words, the

loop‐band‐width does not change significantly (decreases a

little) as the loop switches from 2‐phase to 1‐phase

operation.

Each of the proportional, integral and derivative terms is

a 6‐bit value stored in MTP that is decoded by the IC’s

digital code. This allows the designer to set the converter

bandwidth and phase margin to the desired values.

The compensator transfer function is defined as



































)

(



where ωp1 and ωp2 are configurable poles typically

positioned to filter noise and ripple and roll off the high‐

frequency gain that the KD term creates.

The outputs of the compensator and the phase current

balance block are fed into a digital PWM pulse generator

to generate the PWM pulses for the active phases.

The digital PWM generator has a native time resolution

of 625ps which is combined with digital dithering to

provide an effective PWM resolution of 156.25ps.

This ensures that there is no limit cycling when operating

at the highest switching frequency.

ADAPTIVE TRANSIENT ALGORITHM (ATA)

The IR36021 Adaptive Transient Algorithm (ATA) is a high

speed non‐linear control technique that speeds up the

controller response to loading transients and reduces the

required output bulk capacitance for reduced system cost.

ATA is not very effective for single‐phase rails (loop2). In

addition, it is more effective when used in conjunction

with the load‐line.

A high‐speed digitizer measures both the magnitude and

slope of the error signal to predict the load current

transient. If the magnitude and slope of the error signal

exceed predefined thresholds, the ATA is activated. When

activated, the ATA bypasses the PID control momentarily

during load transients to achieve very wideband closed

loop control and smoothly transitions back to PID control

during steady state load conditions. During ATA operation,

the width of the PWM pulses is not changed. However, the

positions of the pulses are changed. For example, in a

loading transient when ATA is activated, the PWM pulses

come closer in all active phases to compensate for the

undershoot caused by the transient. Figure 25 illustrates

the transient performance improvement provided by the

ATA showing the clear reduction in undershoot and

overshoot and recovery time. Figure 26 is a close up of a

loadstep illustrating the fast reaction time of ATA and how

the algorithm changes the pulse phase relationships. ATA

settings/thresholds can be modified in the GUI. In addition,

it can be disabled if desired. The ATA settings are stored in

MTP memory.

During a load transient overshoot, the ATA can also be

programmed to turn off the low‐side MOSFETS instead of

holding them on. This forces the load current to flow

through the larger forward voltage of the FET body diode

and helps to reduce the overshoot created during a load

release (Figure 27). This is not recommended when there is

no load‐line and there is no steady state load. This is

because unloading creates a Vout overshoot and without

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