IR36021 datasheet(20/41 Pages) IRF

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IR36021

DIGITAL POL BUCK CONTROLLER with I2C AND PMBus

Interface

February 27, 2013 | Rev 3.5

MOSFET DRIVER AND POWIRSTAGE SELECTION

The PWM signals from the active phases of the IR36021

are designed to operate industry standard tri‐state type

drivers or PowIRstage

® devices. The logic operation for the

tri‐state drivers is depicted in Figures 18.

Note that the PWM outputs are tri‐stated whenever the

controller is disabled (EN = low), the shut‐down ramp has

completed or before the soft‐start ramp is initiated.

Figure 18: 3.3V Tri‐state Driver Logic Levels

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The IR36021 VCPU and VRTN pins for each loop are

connected to the load sense pins of each output voltage to

provide true differential remote voltage sensing with high

common‐mode rejection. Each loop has a high bandwidth

error amplifier that generates the error voltage between

this remote sense voltage and the target voltage. The error

voltage is digitized by a fast, high‐precision ADC.

As shown in Figure 19, the Vsen and Vrtn inputs have a

2KΩ pull‐up to an internal 1V rail. This causes some current

flow in the Vsen and Vrtn lines so external impedance

should be kept to a minimum to avoid creating an offset

in the sensed output voltage.

Figure 19: Output Voltage sensing impedance

CURRENT SENSING

The IR36021 provides per phase current sensing to support

accurate Adaptive Voltage Positioning (AVP), current

balancing, and over‐current protection. The differential

current sense scheme supports both lossless inductor DCR

and per phase precision resistor current sensing

techniques.

For DCR sensing, a suitable resistor‐capacitor network of

Rsen and Csen is connected across the inductor in each phase

as shown in Figure 20. The time constant of this RC

network is set to equal the inductor time constant (L/DCR)

such that the voltage across the capacitor Csen is equal to

the voltage across the inductor DCR.

L_out

DCR

R_ISEN

R_IRTN

Rsen

Csen

IRTN

ISEN

Vout

Iphase

Figure 20: DCR Current Sensing

A current proportional to the inductor current in each

phase is generated and used for per phase current

balancing. The individual phase current signals are

summed to arrive at the total current.

The phase currents and total current are quantized by

the monitor ADC and used to implement the current

monitoring and OCP features. The total current is also

summed with the output the output voltage DAC (VID

DAC) to implement the AVP function (load‐line function).

The recommended value for Csen is a 100nF NPO type

capacitor. To prevent undershooting of the output voltage

during load transients, the Rsen resistor can be calculated

by:

DCR

out

sen





Identical resistors (R_ISEN and R_IRTN) are connected to

the ISEN and IRTN pins of each phase for the best common

mode rejection. The required value is:

R_ISEN, R_IRTN = 301Ω, 1% resistor

These components must be placed close to the IR36021

pins.

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