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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM0214 датащи(PDF) 212 Page - STMicroelectronics |
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PM0214 датащи(HTML) 212 Page - STMicroelectronics |
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212 / 245 page  Core peripherals PM0214 212/245 DocID022708 Rev 4 4.4.4 Vector table offset register (VTOR) Address offset: 0x08 Reset value: 0x0000 0000 Required privilege: Privileged 4.4.5 Application interrupt and reset control register (AIRCR) Address offset: 0x0C Reset value: 0xFA05 0000 Required privilege: Privileged The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the processor ignores the write. 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TBLOFF[29:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 76 54 3 21 0 TBLOFF[15:9] Reserved rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept cleared Bits 29:9 TBLOFF: Vector table base offset field. It contains bits [29:9] of the offset of the table base from memory address 0x00000000. When setting TBLOFF, you must align the offset to the number of exception entries in the vector table. The minimum alignment is 128 words. Table alignment requirements mean that bits[8:0] of the table offset are always zero. Bit 29 determines whether the vector table is in the code or SRAM memory region. 0: Code 1: SRAM Note: Bit 29 is sometimes called the TBLBASE bit. Bits 8:0 Reserved, must be kept cleared 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 VECTKEYSTAT[15:0](read)/ VECTKEY[15:0](write) rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 76 54 3 21 0 Reserved PRIGROUP Reserved SYS RESET REQ VECT CLR ACTIVE VECT RESET rrw rw rw w w w |
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