PM0214 datasheet(85/245 Pages) STMICROELECTRONICS

85 / 245 page

DocID022708 Rev 4

85/245

PM0214

The STM32 Cortex-M4 instruction set

244

Condition flags

If S is specified, these instructions:

•

Update the N and Z flags according to the result

•

Can update the C flag during the calculation of operand2 (see Flexible second operand

on page 59)

•

Do not affect the V flag

Examples

AND R9, R2,#0xFF00

ORREQ R2, R0, R5

ANDS R9, R8, #0x19

EORS R7, R11, #0x18181818

BIC R0, R1, #0xab

ORN R7, R11, R14, ROR #4

ORNS R7, R11, R14, ASR #32

3.5.3

ASR, LSL, LSR, ROR, and RRX

Arithmetic shift right, logical shift left, logical shift right, rotate right, and rotate right with

extend.

Syntax

op{S}{cond} Rd, Rm, Rs

op{S}{cond} Rd, Rm, #n

RRX{S}{cond} Rd, Rm

where:

•

‘op’ is one of:

ASR: Arithmetic shift right

LSL: Logical shift left

LSR: Logical shift right

ROR: Rotate right

•

‘S’ is an optional suffix. If S is specified, the condition code flags are updated on the

result of the operation (see Conditional execution on page 64)

•

‘Rd’ is the destination register

•

‘Rm’ is the register holding the value to be shifted

•

‘Rs’ is the register holding the shift length to apply to the value Rm. Only the least

significant byte is used and can be in the range 0 to 255.

•

‘n’ is the shift length. The range of shift lengths depend on the instruction as follows:

ASR: Shift length from 1 to 32

LSL: Shift length from 0 to 31

LSR: Shift length from 1 to 32

ROR: Shift length from 1 to 31

Note:

MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.

PM0214 датащи(PDF) 85 Page - STMicroelectronics

PM0214 датащи(HTML) 85 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL